文件名称:ex1_601
介绍说明－－下载内容均来自于网络，请自行研究使用
该程序可产生周期脉冲，脉冲宽度及周期大小可通过改变相关数值调节。(The program can generate periodic pulse, pulse width and cycle size can be adjusted by changing the correlation value.)
(系统自动生成,下载前可以参看下载内容)
下载文件列表
ex1_601\ex1vhd\clkdiv.asm.rpt
ex1_601\ex1vhd\clkdiv.done
ex1_601\ex1vhd\clkdiv.eda.rpt
ex1_601\ex1vhd\clkdiv.fit.rpt
ex1_601\ex1vhd\clkdiv.fit.smsg
ex1_601\ex1vhd\clkdiv.fit.summary
ex1_601\ex1vhd\clkdiv.flow.rpt
ex1_601\ex1vhd\clkdiv.jdi
ex1_601\ex1vhd\clkdiv.map.rpt
ex1_601\ex1vhd\clkdiv.map.summary
ex1_601\ex1vhd\clkdiv.pin
ex1_601\ex1vhd\clkdiv.pof
ex1_601\ex1vhd\clkdiv.qpf
ex1_601\ex1vhd\clkdiv.qsf
ex1_601\ex1vhd\clkdiv.qws
ex1_601\ex1vhd\clkdiv.sta.rpt
ex1_601\ex1vhd\clkdiv.sta.summary
ex1_601\ex1vhd\clkdiv.vhd
ex1_601\ex1vhd\clkdiv.vhd.bak
ex1_601\ex1vhd\clkdiv_assignment_defaults.qdf
ex1_601\ex1vhd\db\.cmp.kpt
ex1_601\ex1vhd\db\clkdiv.asm.qmsg
ex1_601\ex1vhd\db\clkdiv.asm.rdb
ex1_601\ex1vhd\db\clkdiv.asm_labs.ddb
ex1_601\ex1vhd\db\clkdiv.cbx.xml
ex1_601\ex1vhd\db\clkdiv.cmp.cdb
ex1_601\ex1vhd\db\clkdiv.cmp.hdb
ex1_601\ex1vhd\db\clkdiv.cmp.idb
ex1_601\ex1vhd\db\clkdiv.cmp.logdb
ex1_601\ex1vhd\db\clkdiv.cmp.rdb
ex1_601\ex1vhd\db\clkdiv.cmp0.ddb
ex1_601\ex1vhd\db\clkdiv.db_info
ex1_601\ex1vhd\db\clkdiv.eda.qmsg
ex1_601\ex1vhd\db\clkdiv.fit.qmsg
ex1_601\ex1vhd\db\clkdiv.hier_info
ex1_601\ex1vhd\db\clkdiv.hif
ex1_601\ex1vhd\db\clkdiv.ipinfo
ex1_601\ex1vhd\db\clkdiv.lpc.html
ex1_601\ex1vhd\db\clkdiv.lpc.rdb
ex1_601\ex1vhd\db\clkdiv.lpc.txt
ex1_601\ex1vhd\db\clkdiv.map.cdb
ex1_601\ex1vhd\db\clkdiv.map.hdb
ex1_601\ex1vhd\db\clkdiv.map.logdb
ex1_601\ex1vhd\db\clkdiv.map.qmsg
ex1_601\ex1vhd\db\clkdiv.map.rdb
ex1_601\ex1vhd\db\clkdiv.pplq.rdb
ex1_601\ex1vhd\db\clkdiv.pre_map.hdb
ex1_601\ex1vhd\db\clkdiv.pti_db_list.ddb
ex1_601\ex1vhd\db\clkdiv.root_partition.map.reg_db.cdb
ex1_601\ex1vhd\db\clkdiv.routing.rdb
ex1_601\ex1vhd\db\clkdiv.rtlv.hdb
ex1_601\ex1vhd\db\clkdiv.rtlv_sg.cdb
ex1_601\ex1vhd\db\clkdiv.rtlv_sg_swap.cdb
ex1_601\ex1vhd\db\clkdiv.sgdiff.cdb
ex1_601\ex1vhd\db\clkdiv.sgdiff.hdb
ex1_601\ex1vhd\db\clkdiv.sld_design_entry.sci
ex1_601\ex1vhd\db\clkdiv.sld_design_entry_dsc.sci
ex1_601\ex1vhd\db\clkdiv.smart_action.txt
ex1_601\ex1vhd\db\clkdiv.sta.qmsg
ex1_601\ex1vhd\db\clkdiv.sta.rdb
ex1_601\ex1vhd\db\clkdiv.sta_cmp.5_slow.tdb
ex1_601\ex1vhd\db\clkdiv.tis_db_list.ddb
ex1_601\ex1vhd\db\clkdiv.tmw_info
ex1_601\ex1vhd\db\clkdiv.vpr.ammdb
ex1_601\ex1vhd\db\logic_util_heursitic.dat
ex1_601\ex1vhd\db\prev_cmp_clkdiv.qmsg
ex1_601\ex1vhd\incremental_db\compiled_partitions\clkdiv.db_info
ex1_601\ex1vhd\incremental_db\compiled_partitions\clkdiv.root_partition.map.kpt
ex1_601\ex1vhd\incremental_db\README
ex1_601\ex1vhd\simulation\modelsim\clkdiv.sft
ex1_601\ex1vhd\simulation\modelsim\clkdiv.vo
ex1_601\ex1vhd\simulation\modelsim\clkdiv_modelsim.xrf
ex1_601\ex1vhd\simulation\modelsim\clkdiv_v.sdo
ex1_601\ex1vlg\clkdiv.asm.rpt
ex1_601\ex1vlg\clkdiv.cdf
ex1_601\ex1vlg\clkdiv.done
ex1_601\ex1vlg\clkdiv.eda.rpt
ex1_601\ex1vlg\clkdiv.fit.rpt
ex1_601\ex1vlg\clkdiv.fit.smsg
ex1_601\ex1vlg\clkdiv.fit.summary
ex1_601\ex1vlg\clkdiv.flow.rpt
ex1_601\ex1vlg\clkdiv.jdi
ex1_601\ex1vlg\clkdiv.map.rpt
ex1_601\ex1vlg\clkdiv.map.summary
ex1_601\ex1vlg\clkdiv.pin
ex1_601\ex1vlg\clkdiv.pof
ex1_601\ex1vlg\clkdiv.qpf
ex1_601\ex1vlg\clkdiv.qsf
ex1_601\ex1vlg\clkdiv.qws
ex1_601\ex1vlg\clkdiv.sdc
ex1_601\ex1vlg\clkdiv.sta.rpt
ex1_601\ex1vlg\clkdiv.sta.summary
ex1_601\ex1vlg\clkdiv.v
ex1_601\ex1vlg\clkdiv.v.bak
ex1_601\ex1vlg\clkdiv_assignment_defaults.qdf
ex1_601\ex1vlg\clkdiv_nativelink_simulation.rpt
ex1_601\ex1vlg\db\.cmp.kpt
ex1_601\ex1vlg\db\clkdiv.asm.qmsg
ex1_601\ex1vlg\db\clkdiv.asm.rdb
ex1_601\ex1vlg\db\clkdiv.asm_labs.ddb
ex1_601\ex1vhd\clkdiv.done
ex1_601\ex1vhd\clkdiv.eda.rpt
ex1_601\ex1vhd\clkdiv.fit.rpt
ex1_601\ex1vhd\clkdiv.fit.smsg
ex1_601\ex1vhd\clkdiv.fit.summary
ex1_601\ex1vhd\clkdiv.flow.rpt
ex1_601\ex1vhd\clkdiv.jdi
ex1_601\ex1vhd\clkdiv.map.rpt
ex1_601\ex1vhd\clkdiv.map.summary
ex1_601\ex1vhd\clkdiv.pin
ex1_601\ex1vhd\clkdiv.pof
ex1_601\ex1vhd\clkdiv.qpf
ex1_601\ex1vhd\clkdiv.qsf
ex1_601\ex1vhd\clkdiv.qws
ex1_601\ex1vhd\clkdiv.sta.rpt
ex1_601\ex1vhd\clkdiv.sta.summary
ex1_601\ex1vhd\clkdiv.vhd
ex1_601\ex1vhd\clkdiv.vhd.bak
ex1_601\ex1vhd\clkdiv_assignment_defaults.qdf
ex1_601\ex1vhd\db\.cmp.kpt
ex1_601\ex1vhd\db\clkdiv.asm.qmsg
ex1_601\ex1vhd\db\clkdiv.asm.rdb
ex1_601\ex1vhd\db\clkdiv.asm_labs.ddb
ex1_601\ex1vhd\db\clkdiv.cbx.xml
ex1_601\ex1vhd\db\clkdiv.cmp.cdb
ex1_601\ex1vhd\db\clkdiv.cmp.hdb
ex1_601\ex1vhd\db\clkdiv.cmp.idb
ex1_601\ex1vhd\db\clkdiv.cmp.logdb
ex1_601\ex1vhd\db\clkdiv.cmp.rdb
ex1_601\ex1vhd\db\clkdiv.cmp0.ddb
ex1_601\ex1vhd\db\clkdiv.db_info
ex1_601\ex1vhd\db\clkdiv.eda.qmsg
ex1_601\ex1vhd\db\clkdiv.fit.qmsg
ex1_601\ex1vhd\db\clkdiv.hier_info
ex1_601\ex1vhd\db\clkdiv.hif
ex1_601\ex1vhd\db\clkdiv.ipinfo
ex1_601\ex1vhd\db\clkdiv.lpc.html
ex1_601\ex1vhd\db\clkdiv.lpc.rdb
ex1_601\ex1vhd\db\clkdiv.lpc.txt
ex1_601\ex1vhd\db\clkdiv.map.cdb
ex1_601\ex1vhd\db\clkdiv.map.hdb
ex1_601\ex1vhd\db\clkdiv.map.logdb
ex1_601\ex1vhd\db\clkdiv.map.qmsg
ex1_601\ex1vhd\db\clkdiv.map.rdb
ex1_601\ex1vhd\db\clkdiv.pplq.rdb
ex1_601\ex1vhd\db\clkdiv.pre_map.hdb
ex1_601\ex1vhd\db\clkdiv.pti_db_list.ddb
ex1_601\ex1vhd\db\clkdiv.root_partition.map.reg_db.cdb
ex1_601\ex1vhd\db\clkdiv.routing.rdb
ex1_601\ex1vhd\db\clkdiv.rtlv.hdb
ex1_601\ex1vhd\db\clkdiv.rtlv_sg.cdb
ex1_601\ex1vhd\db\clkdiv.rtlv_sg_swap.cdb
ex1_601\ex1vhd\db\clkdiv.sgdiff.cdb
ex1_601\ex1vhd\db\clkdiv.sgdiff.hdb
ex1_601\ex1vhd\db\clkdiv.sld_design_entry.sci
ex1_601\ex1vhd\db\clkdiv.sld_design_entry_dsc.sci
ex1_601\ex1vhd\db\clkdiv.smart_action.txt
ex1_601\ex1vhd\db\clkdiv.sta.qmsg
ex1_601\ex1vhd\db\clkdiv.sta.rdb
ex1_601\ex1vhd\db\clkdiv.sta_cmp.5_slow.tdb
ex1_601\ex1vhd\db\clkdiv.tis_db_list.ddb
ex1_601\ex1vhd\db\clkdiv.tmw_info
ex1_601\ex1vhd\db\clkdiv.vpr.ammdb
ex1_601\ex1vhd\db\logic_util_heursitic.dat
ex1_601\ex1vhd\db\prev_cmp_clkdiv.qmsg
ex1_601\ex1vhd\incremental_db\compiled_partitions\clkdiv.db_info
ex1_601\ex1vhd\incremental_db\compiled_partitions\clkdiv.root_partition.map.kpt
ex1_601\ex1vhd\incremental_db\README
ex1_601\ex1vhd\simulation\modelsim\clkdiv.sft
ex1_601\ex1vhd\simulation\modelsim\clkdiv.vo
ex1_601\ex1vhd\simulation\modelsim\clkdiv_modelsim.xrf
ex1_601\ex1vhd\simulation\modelsim\clkdiv_v.sdo
ex1_601\ex1vlg\clkdiv.asm.rpt
ex1_601\ex1vlg\clkdiv.cdf
ex1_601\ex1vlg\clkdiv.done
ex1_601\ex1vlg\clkdiv.eda.rpt
ex1_601\ex1vlg\clkdiv.fit.rpt
ex1_601\ex1vlg\clkdiv.fit.smsg
ex1_601\ex1vlg\clkdiv.fit.summary
ex1_601\ex1vlg\clkdiv.flow.rpt
ex1_601\ex1vlg\clkdiv.jdi
ex1_601\ex1vlg\clkdiv.map.rpt
ex1_601\ex1vlg\clkdiv.map.summary
ex1_601\ex1vlg\clkdiv.pin
ex1_601\ex1vlg\clkdiv.pof
ex1_601\ex1vlg\clkdiv.qpf
ex1_601\ex1vlg\clkdiv.qsf
ex1_601\ex1vlg\clkdiv.qws
ex1_601\ex1vlg\clkdiv.sdc
ex1_601\ex1vlg\clkdiv.sta.rpt
ex1_601\ex1vlg\clkdiv.sta.summary
ex1_601\ex1vlg\clkdiv.v
ex1_601\ex1vlg\clkdiv.v.bak
ex1_601\ex1vlg\clkdiv_assignment_defaults.qdf
ex1_601\ex1vlg\clkdiv_nativelink_simulation.rpt
ex1_601\ex1vlg\db\.cmp.kpt
ex1_601\ex1vlg\db\clkdiv.asm.qmsg
ex1_601\ex1vlg\db\clkdiv.asm.rdb
ex1_601\ex1vlg\db\clkdiv.asm_labs.ddb