文件名称:实验1
介绍说明－－下载内容均来自于网络，请自行研究使用
用verilog语言实现译码器,包含数据流文件(Achieve decoder with verilog language, including experimental data stream file)
(系统自动生成,下载前可以参看下载内容)
下载文件列表
extend.v
logic_gates_1.bit
logic_gates_1.v
logic_gates_2.bit
logic_gates_2.v
logic_gates_3.bit
logic_gates_3.v
logic_gates_tb.v
logisim原理图.circ
three_state_gates.bit
three_state_gates.v
logic_gates_1.bit
logic_gates_1.v
logic_gates_2.bit
logic_gates_2.v
logic_gates_3.bit
logic_gates_3.v
logic_gates_tb.v
logisim原理图.circ
three_state_gates.bit
three_state_gates.v