文件名称:delay
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对输入每一路数据进行配置不同时间的延时，在一个存储池内(delay every input channel)
相关搜索： 时间延迟单元
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下载文件列表
delay
delay\test_delay
delay\test_delay\project_1test_delay
delay\test_delay\project_1test_delay\project_1test_delay.cache
delay\test_delay\project_1test_delay\project_1test_delay.cache\compile_simlib
delay\test_delay\project_1test_delay\project_1test_delay.cache\wt
delay\test_delay\project_1test_delay\project_1test_delay.cache\wt\synthesis.wdf
delay\test_delay\project_1test_delay\project_1test_delay.cache\wt\synthesis_details.wdf
delay\test_delay\project_1test_delay\project_1test_delay.cache\wt\webtalk_pa.xml
delay\test_delay\project_1test_delay\project_1test_delay.cache\wt\xsim.wdf
delay\test_delay\project_1test_delay\project_1test_delay.hw
delay\test_delay\project_1test_delay\project_1test_delay.hw\project_1test_delay.lpr
delay\test_delay\project_1test_delay\project_1test_delay.runs
delay\test_delay\project_1test_delay\project_1test_delay.runs\.jobs
delay\test_delay\project_1test_delay\project_1test_delay.runs\.jobs\vrs_config_1.xml
delay\test_delay\project_1test_delay\project_1test_delay.runs\ip_delaynew_0_synth_1
delay\test_delay\project_1test_delay\project_1test_delay.runs\ip_delaynew_0_synth_1\.Vivado_Synthesis.queue.rst
delay\test_delay\project_1test_delay\project_1test_delay.runs\ip_delaynew_0_synth_1\.Xil
delay\test_delay\project_1test_delay\project_1test_delay.runs\ip_delaynew_0_synth_1\.vivado.begin.rst
delay\test_delay\project_1test_delay\project_1test_delay.runs\ip_delaynew_0_synth_1\.vivado.end.rst
delay\test_delay\project_1test_delay\project_1test_delay.runs\ip_delaynew_0_synth_1\ISEWrap.js
delay\test_delay\project_1test_delay\project_1test_delay.runs\ip_delaynew_0_synth_1\ISEWrap.sh
delay\test_delay\project_1test_delay\project_1test_delay.runs\ip_delaynew_0_synth_1\dont_touch.xdc
delay\test_delay\project_1test_delay\project_1test_delay.runs\ip_delaynew_0_synth_1\fsm_encoding.os
delay\test_delay\project_1test_delay\project_1test_delay.runs\ip_delaynew_0_synth_1\gen_run.xml
delay\test_delay\project_1test_delay\project_1test_delay.runs\ip_delaynew_0_synth_1\htr.txt
delay\test_delay\project_1test_delay\project_1test_delay.runs\ip_delaynew_0_synth_1\ip_delaynew_0.dcp
delay\test_delay\project_1test_delay\project_1test_delay.runs\ip_delaynew_0_synth_1\ip_delaynew_0.tcl
delay\test_delay\project_1test_delay\project_1test_delay.runs\ip_delaynew_0_synth_1\ip_delaynew_0.vds
delay\test_delay\project_1test_delay\project_1test_delay.runs\ip_delaynew_0_synth_1\ip_delaynew_0_utilization_synth.pb
delay\test_delay\project_1test_delay\project_1test_delay.runs\ip_delaynew_0_synth_1\ip_delaynew_0_utilization_synth.rpt
delay\test_delay\project_1test_delay\project_1test_delay.runs\ip_delaynew_0_synth_1\project.wdf
delay\test_delay\project_1test_delay\project_1test_delay.runs\ip_delaynew_0_synth_1\rundef.js
delay\test_delay\project_1test_delay\project_1test_delay.runs\ip_delaynew_0_synth_1\runme.bat
delay\test_delay\project_1test_delay\project_1test_delay.runs\ip_delaynew_0_synth_1\runme.log
delay\test_delay\project_1test_delay\project_1test_delay.runs\ip_delaynew_0_synth_1\runme.sh
delay\test_delay\project_1test_delay\project_1test_delay.runs\ip_delaynew_0_synth_1\vivado.jou
delay\test_delay\project_1test_delay\project_1test_delay.runs\ip_delaynew_0_synth_1\vivado.pb
delay\test_delay\project_1test_delay\project_1test_delay.sim
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\.Xil
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\.Xil\Webtalk-15328-user-PC
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\.Xil\Webtalk-15328-user-PC\webtalk
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\compile.bat
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\compile.log
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\elaborate.bat
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\elaborate.log
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\glbl.v
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\ip_delaynew_blk_mem_gen_v8_2_0.mif
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\ip_delaynew_blk_mem_gen_v8_2_0_vivado.coe
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\simulate.bat
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\simulate.log
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\test_bench.tcl
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\test_bench_behav.wdb
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\test_bench_vlog.prj
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\webtalk.jou
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\webtalk.log
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\xelab.pb
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\xsim.dir
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\xsim.dir\blk_mem_gen_v8_2
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\xsim.dir\blk_mem_gen_v8_2\@b@l@k_@m@e@m_@g@e@n_v8_2_mem_module.sdb
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\xsim.dir\blk_mem_gen_v8_2\@b@l@k_@m@e@m_@g@e@n_v8_2_output_stage.sdb
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\xsim.dir\blk_mem_gen_v8_2\@b@l@k_@m@e@m_@g@e@n_v8_2_softecc_output_reg_stage.sdb
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\xsim.dir\blk_mem_gen_v8_2\@s@t@a@t@e_@l@o@g@i@c_v8_2.sdb
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\xsim.dir\blk_mem_gen_v8_2\beh_vlog_ff_ce_clr_v8_2.sdb
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\xsim.dir\blk_mem_gen_v8_2\beh_vlog_ff_clr_v8_2.sdb
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\xsim.dir\blk_mem_gen_v8_2\beh_vlog_ff_pre_v8_2.sdb
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\xsim.dir\blk_mem_gen_v8_2\beh_vlog_muxf7_v8_2.sdb
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\xsim.dir\blk_mem_gen_v8_2\blk_mem_axi_read_wrapper_beh_v8_2.sdb
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\xsim.dir\blk_mem_gen_v8_2\blk_mem_axi_regs_fwd_v8_2.sdb
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\xsim.dir\blk_mem_gen_v8_2\blk_mem_axi_write_wrapper_beh_v8_2.sdb
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\xsim.dir\blk_mem_gen_v8_2\blk_mem_gen_v8_2.sdb
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\xsim.dir\blk_mem_gen_v8_2\ip_delaynew_blk_mem_gen_v8_2_0.sdb
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\xsim.dir\blk_mem_gen_v8_2\read_netlist_v8_2.sdb
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\xsim.dir\blk_mem_gen_v8_2\write_netlist_v8_2.sdb
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\xsim.dir\test_bench_behav
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\xsim.dir\test_bench_behav\Compile_Options.txt
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\xsim.dir\test_bench_behav\test_bench_behav_12900_1508744483.btree
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\xsim.dir\test_bench_behav\webtalk
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\xsim.dir\test_bench_behav\webtalk\.xsim_webtallk.info
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delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\xsim.dir\test_bench_behav\webtalk\usage_statistics_ext_xsim.xml
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\xsim.dir\test_bench_behav\xsim.dbg
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\xsim.dir\test_bench_behav\xsim.mem
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\xsim.dir\test_bench_behav\xsim.reloc
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\xsim.dir\test_bench_behav\xsim.rtti
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\xsim.dir\test_bench_behav\xsim.svtype
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\xsim.dir\test_bench_behav\xsim.type
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\xsim.dir\test_bench_behav\xsim.xdbg
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\xsim.dir\test_bench_behav\xsimcrash.log
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\xsim.dir\test_bench_behav\xsimk.exe
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\xsim.dir\test_bench_behav\xsimkernel.log
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\xsim.dir\xil_defaultlib
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\xsim.dir\xil_defaultlib\align_input.sdb
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\xsim.dir\xil_defaultlib\cast.sdb
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\xsim.dir\xil_defaultlib\control_addr_dps3.sdb
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\xsim.dir\xil_defaultlib\convert_type.sdb
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\xsim.dir\xil_defaultlib\din_adjustment_dps4.sdb
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\xsim.dir\xil_defaultlib\dout_adjustment_dps.sdb
delay\test_delay
delay\test_delay\project_1test_delay
delay\test_delay\project_1test_delay\project_1test_delay.cache
delay\test_delay\project_1test_delay\project_1test_delay.cache\compile_simlib
delay\test_delay\project_1test_delay\project_1test_delay.cache\wt
delay\test_delay\project_1test_delay\project_1test_delay.cache\wt\synthesis.wdf
delay\test_delay\project_1test_delay\project_1test_delay.cache\wt\synthesis_details.wdf
delay\test_delay\project_1test_delay\project_1test_delay.cache\wt\webtalk_pa.xml
delay\test_delay\project_1test_delay\project_1test_delay.cache\wt\xsim.wdf
delay\test_delay\project_1test_delay\project_1test_delay.hw
delay\test_delay\project_1test_delay\project_1test_delay.hw\project_1test_delay.lpr
delay\test_delay\project_1test_delay\project_1test_delay.runs
delay\test_delay\project_1test_delay\project_1test_delay.runs\.jobs
delay\test_delay\project_1test_delay\project_1test_delay.runs\.jobs\vrs_config_1.xml
delay\test_delay\project_1test_delay\project_1test_delay.runs\ip_delaynew_0_synth_1
delay\test_delay\project_1test_delay\project_1test_delay.runs\ip_delaynew_0_synth_1\.Vivado_Synthesis.queue.rst
delay\test_delay\project_1test_delay\project_1test_delay.runs\ip_delaynew_0_synth_1\.Xil
delay\test_delay\project_1test_delay\project_1test_delay.runs\ip_delaynew_0_synth_1\.vivado.begin.rst
delay\test_delay\project_1test_delay\project_1test_delay.runs\ip_delaynew_0_synth_1\.vivado.end.rst
delay\test_delay\project_1test_delay\project_1test_delay.runs\ip_delaynew_0_synth_1\ISEWrap.js
delay\test_delay\project_1test_delay\project_1test_delay.runs\ip_delaynew_0_synth_1\ISEWrap.sh
delay\test_delay\project_1test_delay\project_1test_delay.runs\ip_delaynew_0_synth_1\dont_touch.xdc
delay\test_delay\project_1test_delay\project_1test_delay.runs\ip_delaynew_0_synth_1\fsm_encoding.os
delay\test_delay\project_1test_delay\project_1test_delay.runs\ip_delaynew_0_synth_1\gen_run.xml
delay\test_delay\project_1test_delay\project_1test_delay.runs\ip_delaynew_0_synth_1\htr.txt
delay\test_delay\project_1test_delay\project_1test_delay.runs\ip_delaynew_0_synth_1\ip_delaynew_0.dcp
delay\test_delay\project_1test_delay\project_1test_delay.runs\ip_delaynew_0_synth_1\ip_delaynew_0.tcl
delay\test_delay\project_1test_delay\project_1test_delay.runs\ip_delaynew_0_synth_1\ip_delaynew_0.vds
delay\test_delay\project_1test_delay\project_1test_delay.runs\ip_delaynew_0_synth_1\ip_delaynew_0_utilization_synth.pb
delay\test_delay\project_1test_delay\project_1test_delay.runs\ip_delaynew_0_synth_1\ip_delaynew_0_utilization_synth.rpt
delay\test_delay\project_1test_delay\project_1test_delay.runs\ip_delaynew_0_synth_1\project.wdf
delay\test_delay\project_1test_delay\project_1test_delay.runs\ip_delaynew_0_synth_1\rundef.js
delay\test_delay\project_1test_delay\project_1test_delay.runs\ip_delaynew_0_synth_1\runme.bat
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delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\xsim.dir\blk_mem_gen_v8_2\blk_mem_axi_regs_fwd_v8_2.sdb
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\xsim.dir\blk_mem_gen_v8_2\blk_mem_axi_write_wrapper_beh_v8_2.sdb
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delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\xsim.dir\blk_mem_gen_v8_2\ip_delaynew_blk_mem_gen_v8_2_0.sdb
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\xsim.dir\blk_mem_gen_v8_2\read_netlist_v8_2.sdb
delay\test_delay\project_1test_delay\project_1test_delay.sim\sim_1\behav\xsim.dir\blk_mem_gen_v8_2\write_netlist_v8_2.sdb
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