文件名称:uart_tx
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基于FPGA的串口发送模块设计及仿真,可移植代码-Design and Simulation of serial port sending module based on FPGA，portable code
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下载文件列表
uart_tx
.......\doc
.......\img
.......\prj
.......\...\db
.......\...\..\logic_util_heursitic.dat
.......\...\..\prev_cmp_uart_byte_tx.qmsg
.......\...\..\uart_byte_tx.cbx.xml
.......\...\..\uart_byte_tx.cmp.rdb
.......\...\..\uart_byte_tx.cmp_merge.kpt
.......\...\..\uart_byte_tx.db_info
.......\...\..\uart_byte_tx.hier_info
.......\...\..\uart_byte_tx.hif
.......\...\..\uart_byte_tx.ipinfo
.......\...\..\uart_byte_tx.lpc.html
.......\...\..\uart_byte_tx.lpc.rdb
.......\...\..\uart_byte_tx.lpc.txt
.......\...\..\uart_byte_tx.map.ammdb
.......\...\..\uart_byte_tx.map.bpm
.......\...\..\uart_byte_tx.map.cdb
.......\...\..\uart_byte_tx.map.hdb
.......\...\..\uart_byte_tx.map.kpt
.......\...\..\uart_byte_tx.map.logdb
.......\...\..\uart_byte_tx.map.qmsg
.......\...\..\uart_byte_tx.map.rdb
.......\...\..\uart_byte_tx.map_bb.cdb
.......\...\..\uart_byte_tx.map_bb.hdb
.......\...\..\uart_byte_tx.map_bb.logdb
.......\...\..\uart_byte_tx.pre_map.hdb
.......\...\..\uart_byte_tx.pti_db_list.ddb
.......\...\..\uart_byte_tx.root_partition.map.reg_db.cdb
.......\...\..\uart_byte_tx.rtlv.hdb
.......\...\..\uart_byte_tx.rtlv_sg.cdb
.......\...\..\uart_byte_tx.rtlv_sg_swap.cdb
.......\...\..\uart_byte_tx.sgdiff.cdb
.......\...\..\uart_byte_tx.sgdiff.hdb
.......\...\..\uart_byte_tx.sld_design_entry.sci
.......\...\..\uart_byte_tx.sld_design_entry_dsc.sci
.......\...\..\uart_byte_tx.smart_action.txt
.......\...\..\uart_byte_tx.syn_hier_info
.......\...\..\uart_byte_tx.tis_db_list.ddb
.......\...\..\uart_byte_tx.tmw_info
.......\...\incremental_db
.......\...\..............\README
.......\...\..............\compiled_partitions
.......\...\..............\...................\uart_byte_tx.db_info
.......\...\..............\...................\uart_byte_tx.root_partition.map.cdb
.......\...\..............\...................\uart_byte_tx.root_partition.map.dpi
.......\...\..............\...................\uart_byte_tx.root_partition.map.hbdb.cdb
.......\...\..............\...................\uart_byte_tx.root_partition.map.hbdb.hb_info
.......\...\..............\...................\uart_byte_tx.root_partition.map.hbdb.hdb
.......\...\..............\...................\uart_byte_tx.root_partition.map.hbdb.sig
.......\...\..............\...................\uart_byte_tx.root_partition.map.hdb
.......\...\..............\...................\uart_byte_tx.root_partition.map.kpt
.......\...\ip
.......\...\output_files
.......\...\............\uart_byte_tx.done
.......\...\............\uart_byte_tx.flow.rpt
.......\...\............\uart_byte_tx.map.rpt
.......\...\............\uart_byte_tx.map.summary
.......\...\simulation
.......\...\..........\modelsim
.......\...\..........\........\modelsim.ini
.......\...\..........\........\msim_transcript
.......\...\..........\........\rtl_work
.......\...\..........\........\........\_info
.......\...\..........\........\........\_lib.qdb
.......\...\..........\........\........\_lib1_0.qdb
.......\...\..........\........\........\_lib1_0.qpg
.......\...\..........\........\........\_lib1_0.qtl
.......\...\..........\........\........\_vmake
.......\...\..........\........\uart_byte_tx_run_msim_rtl_verilog.do
.......\...\..........\........\vsim.wlf
.......\...\uart_byte_tx.qpf
.......\...\uart_byte_tx.qsf
.......\...\uart_byte_tx.qws
.......\...\uart_byte_tx_nativelink_simulation.rpt
.......\rtl
.......\...\uart_byte_tx.v
.......\...\uart_byte_tx.v.bak
.......\testbench
.......\.........\uart_byte_tx_tb.v
.......\.........\uart_byte_tx_tb.v.bak