文件名称:seg7_verilog

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [ASM] [源码]
  • 上传时间:
  • 2017-04-20
  • 文件大小:
  • 3.26mb
  • 下载次数:
  • 0次
  • 提 供 者:
  • 曹**
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

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七段式LED数码管驱动,Verilog源码,FPGA开发学习。硬件描述语言基础学习。-LED driver
(系统自动生成,下载前可以参看下载内容)

下载文件列表





seg7_verilog\db\logic_util_heursitic.dat

............\..\prev_cmp_seg7.asm.qmsg

............\..\prev_cmp_seg7.eda.qmsg

............\..\prev_cmp_seg7.fit.qmsg

............\..\prev_cmp_seg7.map.qmsg

............\..\prev_cmp_seg7.qmsg

............\..\prev_cmp_seg7.sta.qmsg

............\..\prev_cmp_seg7.tan.qmsg

............\..\seg7.db_info

............\..\seg7.sld_design_entry.sci

............\..\seg7_global_asgn_op.abo

............\incremental_db\compiled_partitions\seg7.db_info

............\..............\...................\seg7.root_partition.cmp.atm

............\..............\...................\seg7.root_partition.cmp.dfp

............\..............\...................\seg7.root_partition.cmp.hdbx

............\..............\...................\seg7.root_partition.cmp.kpt

............\..............\...................\seg7.root_partition.cmp.logdb

............\..............\...................\seg7.root_partition.cmp.rcf

............\..............\...................\seg7.root_partition.map.atm

............\..............\...................\seg7.root_partition.map.dpi

............\..............\...................\seg7.root_partition.map.hdbx

............\..............\...................\seg7.root_partition.map.kpt

............\..............\README

............\seg7.asm.rpt

............\seg7.cdf

............\seg7.done

............\seg7.dpf

............\seg7.eda.rpt

............\seg7.fit.rpt

............\seg7.fit.smsg

............\seg7.fit.summary

............\seg7.flow.rpt

............\seg7.map.rpt

............\seg7.map.summary

............\seg7.pin

............\seg7.pof

............\seg7.qpf

............\seg7.qsf

............\seg7.qws

............\seg7.sdc

............\seg7.sof

............\seg7.sta.rpt

............\seg7.sta.summary

............\seg7.tan.rpt

............\seg7.tan.summary

............\seg7.v

............\seg7_assignment_defaults.qdf

............\seg7_nativelink_simulation.rpt

............\.imulation\modelsim\altera_mf.v

............\..........\........\cyclone\@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s\verilog.asm

............\..........\........\.......\..........................................\_primary.dat

............\..........\........\.......\..........................................\_primary.vhd

............\..........\........\.......\..............m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n\verilog.asm

............\..........\........\.......\...............................................\_primary.dat

............\..........\........\.......\...............................................\_primary.vhd

............\..........\........\.......\...................m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n\verilog.asm

............\..........\........\.......\...........................................................\_primary.dat

............\..........\........\.......\...........................................................\_primary.vhd

............\..........\........\.......\.c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e\verilog.asm

............\..........\........\.......\................................\_primary.dat

............\..........\........\.......\................................\_primary.vhd

............\..........\........\.......\.m@f_cycloneiii_pll\verilog.asm

............\..........\........\.......\...................\_primary.dat

............\..........\........\.......\...................\_primary.vhd

............\..........\........\.......\.....pll_reg\verilog.asm

............\..........\........\.......\............\_primary.dat

............\..........\........\.......\............\_primary.vhd

............\..........\........\.......\.....stratixiii_pll\verilog.asm

............\..........\........\.......\...................\_primary.dat

............\..........\........\.......\...................\_primary.vhd

............\..........\........\.......\.............._pll\verilog.asm

............\..........\........\.......\..................\_primary.dat

............\..........\........\.......\..................\_primary.vhd

............\..........\........\.......\............

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