文件名称:lab3_1

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • 上传时间:
  • 2016-07-21
  • 文件大小:
  • 658kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • 刘*
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

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VHDL利用四位拨盘输入数据,输入两个数,显示于数码管,另两个数码管显示其取反,四个数字再留个数码管上以一秒为周期左移-VHDL use four dial input data, input two numbers displayed on the digital control, the other two digital display its negation, then leave a four-digit digital tube left at one-second cycle
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下载文件列表





lab3_1

......\db

......\..\add_sub_lsh.tdf

......\..\add_sub_msh.tdf

......\..\lab3_1.asm.qmsg

......\..\lab3_1.cbx.xml

......\..\lab3_1.cmp.bpm

......\..\lab3_1.cmp.cdb

......\..\lab3_1.cmp.ecobp

......\..\lab3_1.cmp.hdb

......\..\lab3_1.cmp.logdb

......\..\lab3_1.cmp.rdb

......\..\lab3_1.cmp.tdb

......\..\lab3_1.cmp0.ddb

......\..\lab3_1.db_info

......\..\lab3_1.eco.cdb

......\..\lab3_1.eds_overflow

......\..\lab3_1.fit.qmsg

......\..\lab3_1.fnsim.hdb

......\..\lab3_1.fnsim.qmsg

......\..\lab3_1.hier_info

......\..\lab3_1.hif

......\..\lab3_1.map.bpm

......\..\lab3_1.map.cdb

......\..\lab3_1.map.ecobp

......\..\lab3_1.map.hdb

......\..\lab3_1.map.logdb

......\..\lab3_1.map.qmsg

......\..\lab3_1.map_bb.cdb

......\..\lab3_1.map_bb.hdb

......\..\lab3_1.map_bb.hdbx

......\..\lab3_1.map_bb.logdb

......\..\lab3_1.pre_map.cdb

......\..\lab3_1.pre_map.hdb

......\..\lab3_1.psp

......\..\lab3_1.root_partition.cmp.atm

......\..\lab3_1.root_partition.cmp.dfp

......\..\lab3_1.root_partition.cmp.hdbx

......\..\lab3_1.root_partition.cmp.logdb

......\..\lab3_1.root_partition.cmp.rcf

......\..\lab3_1.root_partition.map.atm

......\..\lab3_1.root_partition.map.hdbx

......\..\lab3_1.root_partition.map.info

......\..\lab3_1.rtlv.hdb

......\..\lab3_1.rtlv_sg.cdb

......\..\lab3_1.rtlv_sg_swap.cdb

......\..\lab3_1.sgdiff.cdb

......\..\lab3_1.sgdiff.hdb

......\..\lab3_1.signalprobe.cdb

......\..\lab3_1.sim.cvwf

......\..\lab3_1.sim.hdb

......\..\lab3_1.sim.qmsg

......\..\lab3_1.sim.rdb

......\..\lab3_1.simfam

......\..\lab3_1.sld_design_entry.sci

......\..\lab3_1.sld_design_entry_dsc.sci

......\..\lab3_1.syn_hier_info

......\..\lab3_1.tan.qmsg

......\..\lab3_1.tis_db_list.ddb

......\..\lab3_1.tmw_info

......\..\mux_1hc.tdf

......\..\prev_cmp_lab3_1.asm.qmsg

......\..\prev_cmp_lab3_1.fit.qmsg

......\..\prev_cmp_lab3_1.map.qmsg

......\..\prev_cmp_lab3_1.qmsg

......\..\prev_cmp_lab3_1.tan.qmsg

......\..\wed.wsf

......\lab3_1.asm.rpt

......\lab3_1.done

......\lab3_1.fit.rpt

......\lab3_1.fit.smsg

......\lab3_1.fit.summary

......\lab3_1.flow.rpt

......\lab3_1.map.rpt

......\lab3_1.map.summary

......\lab3_1.pin

......\lab3_1.pof

......\lab3_1.qpf

......\lab3_1.qsf

......\lab3_1.qws

......\lab3_1.sim.rpt

......\lab3_1.sof

......\lab3_1.tan.rpt

......\lab3_1.tan.summary

......\lab3_1.vhd

......\lab3_1.vhd.bak

......\lab3_1.vwf

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