文件名称:nand_data
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this program is done in verilog hdl and it is program of AND gate DATA level modeling program-this program is done in verilog hdl and it is program of AND gate DATA level modeling program
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下载文件列表
nand_data\db\logic_util_heursitic.dat
.........\..\nand_data.ae.hdb
.........\..\nand_data.asm.qmsg
.........\..\nand_data.asm.rdb
.........\..\nand_data.cbx.xml
.........\..\nand_data.cmp.cdb
.........\..\nand_data.cmp.hdb
.........\..\nand_data.cmp.logdb
.........\..\nand_data.cmp.rdb
.........\..\nand_data.cmp0.ddb
.........\..\nand_data.db_info
.........\..\nand_data.eda.qmsg
.........\..\nand_data.fit.qmsg
.........\..\nand_data.hier_info
.........\..\nand_data.hif
.........\..\nand_data.ipinfo
.........\..\nand_data.lpc.html
.........\..\nand_data.lpc.rdb
.........\..\nand_data.lpc.txt
.........\..\nand_data.map.cdb
.........\..\nand_data.map.hdb
.........\..\nand_data.map.logdb
.........\..\nand_data.map.qmsg
.........\..\nand_data.map.rdb
.........\..\nand_data.pre_map.cdb
.........\..\nand_data.pre_map.hdb
.........\..\nand_data.pti_db_list.ddb
.........\..\nand_data.root_partition.map.reg_db.cdb
.........\..\nand_data.rpp.qmsg
.........\..\nand_data.rtlv.hdb
.........\..\nand_data.rtlv_sg.cdb
.........\..\nand_data.rtlv_sg_swap.cdb
.........\..\nand_data.sgate.rvd
.........\..\nand_data.sgate_sm.rvd
.........\..\nand_data.sgdiff.cdb
.........\..\nand_data.sgdiff.hdb
.........\..\nand_data.sld_design_entry.sci
.........\..\nand_data.sld_design_entry_dsc.sci
.........\..\nand_data.smart_action.txt
.........\..\nand_data.sta.qmsg
.........\..\nand_data.sta.rdb
.........\..\nand_data.syn_hier_info
.........\..\nand_data.tis_db_list.ddb
.........\..\nand_data.tmw_info
.........\..\prev_cmp_nand_data.qmsg
.........\incremental_db\compiled_partitions\nand_data.db_info
.........\..............\...................\nand_data.root_partition.map.kpt
.........\..............\README
.........\nand_data.asm.rpt
.........\nand_data.done
.........\nand_data.eda.rpt
.........\nand_data.fit.rpt
.........\nand_data.fit.summary
.........\nand_data.flow.rpt
.........\nand_data.jdi
.........\nand_data.map.rpt
.........\nand_data.map.summary
.........\nand_data.pin
.........\nand_data.pof
.........\nand_data.qpf
.........\nand_data.qsf
.........\nand_data.qws
.........\nand_data.sta.rpt
.........\nand_data.sta.summary
.........\nand_data.v
.........\nand_data.v.bak
.........\nand_data_assignment_defaults.qdf
.........\nand_data_nativelink_simulation.rpt
.........\simulation\modelsim\modelsim.ini
.........\..........\........\msim_transcript
.........\..........\........\nand_data.sft
.........\..........\........\nand_data.vo
.........\..........\........\nand_data_modelsim.xrf
.........\..........\........\nand_data_run_msim_rtl_verilog.do
.........\..........\........\nand_data_run_msim_rtl_verilog.do.bak
.........\..........\........\nand_data_run_msim_rtl_verilog.do.bak1
.........\..........\........\nand_data_run_msim_rtl_verilog.do.bak2
.........\..........\........\nand_data_v.sdo
.........\..........\........\rtl_work\nand_data\verilog.prw
.........\..........\........\........\.........\verilog.psm
.........\..........\........\........\.........\_primary.dat
.........\..........\........\........\.........\_primary.dbs
.........\..........\........\........\.........\_primary.vhd
.........\..........\........\........\_info
.........\..........\........\........\_vmake
.........\..........\........\vsim.wlf
.........\..........\........\rtl_work\nand_data
.........\..........\........\........\_temp
.........\..........\........\rtl_work
.........\incremental_db\compiled_partitions
.........\simulation\modelsim
.........\db
.........\incremental_db
.........\simulation
nand_data