文件名称:nand_gate

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [VHDL] [源码]
  • 上传时间:
  • 2016-07-12
  • 文件大小:
  • 123kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • het***
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

this program is done in verilog hdl and it is program of NAND gate gate level modeling program-this program is done in verilog hdl and it is program of NAND gate gate level modeling program 
(系统自动生成,下载前可以参看下载内容)

下载文件列表





nand_gate\db\logic_util_heursitic.dat

.........\..\nand_gate.asm.qmsg

.........\..\nand_gate.asm.rdb

.........\..\nand_gate.cbx.xml

.........\..\nand_gate.cmp.cdb

.........\..\nand_gate.cmp.hdb

.........\..\nand_gate.cmp.logdb

.........\..\nand_gate.cmp.rdb

.........\..\nand_gate.cmp0.ddb

.........\..\nand_gate.db_info

.........\..\nand_gate.eda.qmsg

.........\..\nand_gate.fit.qmsg

.........\..\nand_gate.hier_info

.........\..\nand_gate.hif

.........\..\nand_gate.ipinfo

.........\..\nand_gate.lpc.html

.........\..\nand_gate.lpc.rdb

.........\..\nand_gate.lpc.txt

.........\..\nand_gate.map.cdb

.........\..\nand_gate.map.hdb

.........\..\nand_gate.map.logdb

.........\..\nand_gate.map.qmsg

.........\..\nand_gate.map.rdb

.........\..\nand_gate.pre_map.hdb

.........\..\nand_gate.pti_db_list.ddb

.........\..\nand_gate.root_partition.map.reg_db.cdb

.........\..\nand_gate.rpp.qmsg

.........\..\nand_gate.rtlv.hdb

.........\..\nand_gate.rtlv_sg.cdb

.........\..\nand_gate.rtlv_sg_swap.cdb

.........\..\nand_gate.sgate.rvd

.........\..\nand_gate.sgate_sm.rvd

.........\..\nand_gate.sgdiff.cdb

.........\..\nand_gate.sgdiff.hdb

.........\..\nand_gate.sld_design_entry.sci

.........\..\nand_gate.sld_design_entry_dsc.sci

.........\..\nand_gate.smart_action.txt

.........\..\nand_gate.sta.qmsg

.........\..\nand_gate.sta.rdb

.........\..\nand_gate.sta_cmp.4_slow.tdb

.........\..\nand_gate.syn_hier_info

.........\..\nand_gate.tis_db_list.ddb

.........\..\nand_gate.tmw_info

.........\..\prev_cmp_nand_gate.qmsg

.........\incremental_db\compiled_partitions\nand_gate.db_info

.........\..............\...................\nand_gate.root_partition.map.kpt

.........\..............\README

.........\nand_gate.asm.rpt

.........\nand_gate.done

.........\nand_gate.eda.rpt

.........\nand_gate.fit.rpt

.........\nand_gate.fit.summary

.........\nand_gate.flow.rpt

.........\nand_gate.jdi

.........\nand_gate.map.rpt

.........\nand_gate.map.summary

.........\nand_gate.pin

.........\nand_gate.pof

.........\nand_gate.qpf

.........\nand_gate.qsf

.........\nand_gate.qws

.........\nand_gate.sta.rpt

.........\nand_gate.sta.summary

.........\nand_gate.v

.........\nand_gate.v.bak

.........\nand_gate_assignment_defaults.qdf

.........\nand_gate_nativelink_simulation.rpt

.........\nand_test.v

.........\nand_test.v.bak

.........\simulation\modelsim\modelsim.ini

.........\..........\........\msim_transcript

.........\..........\........\nand_gate.sft

.........\..........\........\nand_gate.vo

.........\..........\........\nand_gate_modelsim.xrf

.........\..........\........\nand_gate_run_msim_rtl_verilog.do

.........\..........\........\nand_gate_run_msim_rtl_verilog.do.bak

.........\..........\........\nand_gate_run_msim_rtl_verilog.do.bak1

.........\..........\........\nand_gate_run_msim_rtl_verilog.do.bak2

.........\..........\........\nand_gate_v.sdo

.........\..........\........\rtl_work\nand_gate\verilog.prw

.........\..........\........\........\.........\verilog.psm

.........\..........\........\........\.........\_primary.dat

.........\..........\........\........\.........\_primary.dbs

.........\..........\........\........\.........\_primary.vhd

.........\..........\........\........\.....test\verilog.prw

.........\..........\........\........\.........\verilog.psm

.........\..........\........\........\.........\_primary.dat

.........\..........\........\........\.........\_primary.dbs

.........\..........\........\........\.........\_primary.vhd

.........\..........\........\........\_info

.........\..........\........\........\_vmake

.........\..........\........\vsim.wlf

.........\..........\........\rtl_work\nand_gate

.........\..........\........\........\nand_test

.........\..........\........\........\_temp

.........\..........\........\rtl_work

.........\incremental_db\compiled_partitions

.........\simulation\modelsim

.........\db

.........\incremental_db

相关说明

  • 本站资源为会员上传分享交流与学习,如有侵犯您的权益,请联系我们删除.
  • 本站是交换下载平台,提供交流渠道,下载内容来自于网络,除下载问题外,其它问题请自行百度更多...
  • 请直接用浏览器下载本站内容,不要使用迅雷之类的下载软件,用WinRAR最新版进行解压.
  • 如果您发现内容无法下载,请稍后再次尝试;或者到消费记录里找到下载记录反馈给我们.
  • 下载后发现下载的内容跟说明不相乎,请到消费记录里找到下载记录反馈给我们,经确认后退回积分.
  • 如下载前有疑问,可以通过点击"提供者"的名字,查看对方的联系方式,联系对方咨询.

相关评论

暂无评论内容.

发表评论

*主  题:
*内  容:
*验 证 码:

源码中国 www.ymcn.org