文件名称:and_data
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this program is done in verilog hdl and it is program of AND gate DATA level modeling program-this program is done in verilog hdl and it is program of AND gate DATA level modeling program
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下载文件列表
and_data\and_data.asm.rpt
........\and_data.done
........\and_data.eda.rpt
........\and_data.fit.rpt
........\and_data.fit.summary
........\and_data.flow.rpt
........\and_data.jdi
........\and_data.map.rpt
........\and_data.map.summary
........\and_data.pin
........\and_data.pof
........\and_data.qpf
........\and_data.qsf
........\and_data.qws
........\and_data.sta.rpt
........\and_data.sta.summary
........\and_data.v
........\and_data.v.bak
........\and_data_assignment_defaults.qdf
........\and_data_nativelink_simulation.rpt
........\db\add_sub_09c.tdf
........\..\alt_u_div_fje.tdf
........\..\and_data.asm.qmsg
........\..\and_data.asm.rdb
........\..\and_data.cbx.xml
........\..\and_data.cmp.cdb
........\..\and_data.cmp.hdb
........\..\and_data.cmp.logdb
........\..\and_data.cmp.rdb
........\..\and_data.cmp0.ddb
........\..\and_data.db_info
........\..\and_data.eda.qmsg
........\..\and_data.fit.qmsg
........\..\and_data.hier_info
........\..\and_data.hif
........\..\and_data.ipinfo
........\..\and_data.lpc.html
........\..\and_data.lpc.rdb
........\..\and_data.lpc.txt
........\..\and_data.map.cdb
........\..\and_data.map.hdb
........\..\and_data.map.logdb
........\..\and_data.map.qmsg
........\..\and_data.map.rdb
........\..\and_data.pre_map.hdb
........\..\and_data.pti_db_list.ddb
........\..\and_data.root_partition.map.reg_db.cdb
........\..\and_data.rtlv.hdb
........\..\and_data.rtlv_sg.cdb
........\..\and_data.rtlv_sg_swap.cdb
........\..\and_data.sgdiff.cdb
........\..\and_data.sgdiff.hdb
........\..\and_data.sld_design_entry.sci
........\..\and_data.sld_design_entry_dsc.sci
........\..\and_data.smart_action.txt
........\..\and_data.sta.qmsg
........\..\and_data.sta.rdb
........\..\and_data.sta_cmp.4_slow.tdb
........\..\and_data.syn_hier_info
........\..\and_data.tis_db_list.ddb
........\..\and_data.tmw_info
........\..\logic_util_heursitic.dat
........\..\lpm_divide_5pl.tdf
........\..\prev_cmp_and_data.qmsg
........\..\sign_div_unsign_1kh.tdf
........\incremental_db\compiled_partitions\and_data.db_info
........\..............\...................\and_data.root_partition.map.kpt
........\..............\README
........\or_data.v
........\simulation\modelsim\and_data.sft
........\..........\........\and_data.vo
........\..........\........\and_data_modelsim.xrf
........\..........\........\and_data_run_msim_rtl_verilog.do
........\..........\........\and_data_run_msim_rtl_verilog.do.bak
........\..........\........\and_data_run_msim_rtl_verilog.do.bak1
........\..........\........\and_data_v.sdo
........\..........\........\modelsim.ini
........\..........\........\msim_transcript
........\..........\........\rtl_work\and_data\verilog.prw
........\..........\........\........\........\verilog.psm
........\..........\........\........\........\_primary.dat
........\..........\........\........\........\_primary.dbs
........\..........\........\........\........\_primary.vhd
........\..........\........\........\_info
........\..........\........\........\_vmake
........\..........\........\vsim.wlf
........\..........\........\rtl_work\and_data
........\..........\........\........\_temp
........\..........\........\rtl_work
........\incremental_db\compiled_partitions
........\simulation\modelsim
........\db
........\incremental_db
........\simulation
and_data