文件名称:and_gate
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this program is done in verilog hdl and it is program of AND gate gate level modeling program-this program is done in verilog hdl and it is program of AND gate gate level modeling program
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下载文件列表
and_gate\and_gate.asm.rpt
........\and_gate.done
........\and_gate.eda.rpt
........\and_gate.fit.rpt
........\and_gate.fit.summary
........\and_gate.flow.rpt
........\and_gate.jdi
........\and_gate.map.rpt
........\and_gate.map.summary
........\and_gate.pin
........\and_gate.pof
........\and_gate.qpf
........\and_gate.qsf
........\and_gate.qws
........\and_gate.sta.rpt
........\and_gate.sta.summary
........\and_gate.v
........\and_gate_assignment_defaults.qdf
........\and_gate_nativelink_simulation.rpt
........\and_test.v
........\and_test.v.bak
........\db\and_gate.ae.hdb
........\..\and_gate.asm.qmsg
........\..\and_gate.asm.rdb
........\..\and_gate.cbx.xml
........\..\and_gate.cmp.cdb
........\..\and_gate.cmp.hdb
........\..\and_gate.cmp.logdb
........\..\and_gate.cmp.rdb
........\..\and_gate.cmp0.ddb
........\..\and_gate.db_info
........\..\and_gate.eda.qmsg
........\..\and_gate.fit.qmsg
........\..\and_gate.hier_info
........\..\and_gate.hif
........\..\and_gate.ipinfo
........\..\and_gate.lpc.html
........\..\and_gate.lpc.rdb
........\..\and_gate.lpc.txt
........\..\and_gate.map.cdb
........\..\and_gate.map.hdb
........\..\and_gate.map.logdb
........\..\and_gate.map.qmsg
........\..\and_gate.map.rdb
........\..\and_gate.pre_map.hdb
........\..\and_gate.pti_db_list.ddb
........\..\and_gate.root_partition.map.reg_db.cdb
........\..\and_gate.rpp.qmsg
........\..\and_gate.rtlv.hdb
........\..\and_gate.rtlv_sg.cdb
........\..\and_gate.rtlv_sg_swap.cdb
........\..\and_gate.sgate.rvd
........\..\and_gate.sgate_sm.rvd
........\..\and_gate.sgdiff.cdb
........\..\and_gate.sgdiff.hdb
........\..\and_gate.sld_design_entry.sci
........\..\and_gate.sld_design_entry_dsc.sci
........\..\and_gate.smart_action.txt
........\..\and_gate.sta.qmsg
........\..\and_gate.sta.rdb
........\..\and_gate.sta_cmp.4_slow.tdb
........\..\and_gate.syn_hier_info
........\..\and_gate.tis_db_list.ddb
........\..\logic_util_heursitic.dat
........\..\prev_cmp_and_gate.qmsg
........\incremental_db\compiled_partitions\and_gate.db_info
........\..............\...................\and_gate.root_partition.map.kpt
........\..............\README
........\simulation\modelsim\and_gate.sft
........\..........\........\and_gate.vo
........\..........\........\and_gate_modelsim.xrf
........\..........\........\and_gate_run_msim_gate_verilog.do
........\..........\........\and_gate_run_msim_rtl_verilog.do
........\..........\........\and_gate_run_msim_rtl_verilog.do.bak
........\..........\........\and_gate_run_msim_rtl_verilog.do.bak1
........\..........\........\and_gate_run_msim_rtl_verilog.do.bak10
........\..........\........\and_gate_run_msim_rtl_verilog.do.bak11
........\..........\........\and_gate_run_msim_rtl_verilog.do.bak2
........\..........\........\and_gate_run_msim_rtl_verilog.do.bak3
........\..........\........\and_gate_run_msim_rtl_verilog.do.bak4
........\..........\........\and_gate_run_msim_rtl_verilog.do.bak5
........\..........\........\and_gate_run_msim_rtl_verilog.do.bak6
........\..........\........\and_gate_run_msim_rtl_verilog.do.bak7
........\..........\........\and_gate_run_msim_rtl_verilog.do.bak8
........\..........\........\and_gate_run_msim_rtl_verilog.do.bak9
........\..........\........\and_gate_v.sdo
........\..........\........\gate_work\and_gate\verilog.prw
........\..........\........\.........\........\verilog.psm
........\..........\........\.........\........\_primary.dat
........\..........\........\.........\........\_primary.dbs
........\..........\........\.........\........\_primary.vhd
........\..........\........\.........\_info
........\..........\........\.........\_vmake
........\..........\........\msim_transcript
........\..........\........\rtl_work\and_gate\verilog.prw
........\..........\........\........\........\verilog.psm
........\..........\........\........\........\_primary.dat
........\..........\........\........\........\_primary.dbs
........\..........\........\........\........\_primary.vhd
........\..........\........\........\_info