文件名称:FPGA_Project
介绍说明－－下载内容均来自于网络，请自行研究使用
USB 2.0的数据传输verilog程序，采用的是slave状态机实现其功能。其中包括读、写功能
-USB 2.0 data transfer verilog program, using the slave state machine functionality. Including reading and writing functions
-USB 2.0 data transfer verilog program, using the slave state machine functionality. Including reading and writing functions
(系统自动生成,下载前可以参看下载内容)
下载文件列表
FPGA_Project\db\altsyncram_0q14.tdf
............\..\cmpr_5cc.tdf
............\..\cmpr_6cc.tdf
............\..\cmpr_8cc.tdf
............\..\cmpr_9cc.tdf
............\..\cntr_02j.tdf
............\..\cntr_0ci.tdf
............\..\cntr_7ai.tdf
............\..\cntr_gui.tdf
............\..\cntr_sbi.tdf
............\..\decode_rqf.tdf
............\..\fpga_master.amm.cdb
............\..\fpga_master.asm.qmsg
............\..\fpga_master.asm.rdb
............\..\fpga_master.asm_labs.ddb
............\..\fpga_master.cbx.xml
............\..\fpga_master.cmp.bpm
............\..\fpga_master.cmp.cdb
............\..\fpga_master.cmp.hdb
............\..\fpga_master.cmp.kpt
............\..\fpga_master.cmp.logdb
............\..\fpga_master.cmp.rdb
............\..\fpga_master.cmp_merge.kpt
............\..\fpga_master.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
............\..\fpga_master.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd
............\..\fpga_master.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd
............\..\fpga_master.db_info
............\..\fpga_master.eda.qmsg
............\..\fpga_master.fit.qmsg
............\..\fpga_master.hier_info
............\..\fpga_master.hif
............\..\fpga_master.idb.cdb
............\..\fpga_master.lpc.html
............\..\fpga_master.lpc.rdb
............\..\fpga_master.lpc.txt
............\..\fpga_master.map.bpm
............\..\fpga_master.map.cdb
............\..\fpga_master.map.hdb
............\..\fpga_master.map.kpt
............\..\fpga_master.map.logdb
............\..\fpga_master.map.qmsg
............\..\fpga_master.map_bb.cdb
............\..\fpga_master.map_bb.hdb
............\..\fpga_master.map_bb.logdb
............\..\fpga_master.pre_map.cdb
............\..\fpga_master.pre_map.hdb
............\..\fpga_master.rtlv.hdb
............\..\fpga_master.rtlv_sg.cdb
............\..\fpga_master.rtlv_sg_swap.cdb
............\..\fpga_master.sgdiff.cdb
............\..\fpga_master.sgdiff.hdb
............\..\fpga_master.sld_design_entry.sci
............\..\fpga_master.sld_design_entry_dsc.sci
............\..\fpga_master.smart_action.txt
............\..\fpga_master.sta.qmsg
............\..\fpga_master.sta.rdb
............\..\fpga_master.sta_cmp.8_slow_1200mv_85c.tdb
............\..\fpga_master.syn_hier_info
............\..\fpga_master.tiscmp.fastest_slow_1200mv_0c.ddb
............\..\fpga_master.tiscmp.fastest_slow_1200mv_85c.ddb
............\..\fpga_master.tiscmp.fast_1200mv_0c.ddb
............\..\fpga_master.tiscmp.slow_1200mv_0c.ddb
............\..\fpga_master.tiscmp.slow_1200mv_85c.ddb
............\..\fpga_master.tis_db_list.ddb
............\..\logic_util_heursitic.dat
............\..\mux_aoc.tdf
............\..\prev_cmp_fpga_master.qmsg
............\fpga_master.asm.rpt
............\fpga_master.bdf
............\fpga_master.bsf
............\fpga_master.cdf
............\fpga_master.done
............\fpga_master.eda.rpt
............\fpga_master.fit.rpt
............\fpga_master.fit.smsg
............\fpga_master.fit.summary
............\fpga_master.flow.rpt
............\fpga_master.jdi
............\fpga_master.map.rpt
............\fpga_master.map.summary
............\fpga_master.merge.rpt
............\fpga_master.pin
............\fpga_master.pof
............\fpga_master.qpf
............\fpga_master.qsf
............\fpga_master.qsf.bak
............\fpga_master.sof
............\fpga_master.sta.rpt
............\fpga_master.sta.summary
............\fpga_master.vhd
............\fpga_master.vhd.bak
............\fpga_master_assignment_defaults.qdf
............\fpga_master_sync.bdf
............\greybox_tmp\cbx_args.txt
............\incremental_db\compiled_partitions\fpga_master.autoh_e4eb1.map.cdb
............\..............\...................\fpga_master.autoh_e4eb1.map.dpi
............\..............\...................\fpga_master.autoh_e4eb1.map.hdb
............\..............\...................\fpga_master.autoh_e4eb1.map.kpt
............\..............\...................\fpga_master.autoh_e4eb1.map.logdb
............\..............\...................\fpga_master.autol_7d8f1.map.cdb