文件名称:VHDL-Design-of-31-bit-Pipelined-Adder

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [HTML]
  • 上传时间:
  • 2016-05-31
  • 文件大小:
  • 215kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • hooman h********
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The design runs at 316.46 MHz and uses 125 LEs.
(系统自动生成,下载前可以参看下载内容)

下载文件列表





VHDL Design of 31-bit Pipelined Adder\adder.bld

.....................................\adder.cmd_log

.....................................\adder.lso

.....................................\adder.ncd

.....................................\adder.ngc

.....................................\adder.ngd

.....................................\adder.ngr

.....................................\adder.pad

.....................................\adder.par

.....................................\adder.pcf

.....................................\adder.prj

.....................................\adder.ptwx

.....................................\adder.stx

.....................................\adder.syr

.....................................\adder.twr

.....................................\adder.twx

.....................................\adder.unroutes

.....................................\adder.vhd

.....................................\adder.xpi

.....................................\adder.xst

.....................................\adder_envsettings.html

.....................................\adder_guide.ncd

.....................................\adder_map.map

.....................................\adder_map.mrp

.....................................\adder_map.ncd

.....................................\adder_map.ngm

.....................................\adder_map.xrpt

.....................................\adder_ngdbuild.xrpt

.....................................\adder_pad.csv

.....................................\adder_pad.txt

.....................................\adder_par.xrpt

.....................................\adder_stx_beh.prj

.....................................\adder_summary.html

.....................................\adder_summary.xml

.....................................\adder_usage.xml

.....................................\adder_vhdl.prj

.....................................\adder_xpa.log

.....................................\adder_xst.xrpt

.....................................\example2_17.gise

.....................................\example2_17.xise

.....................................\fuse.xmsgs

.....................................\iseconfig\adder.xreport

.....................................\.........\example2_17.projectmgr

.....................................\..im\temp\adder.vdb

.....................................\webtalk_pn.xml

.....................................\xilinxsim.ini

.....................................\.lnx_auto_0_xdb\cst.xbcd

.....................................\.st\work\hdllib.ref

.....................................\...\....\hdpdeps.ref

.....................................\...\....\sub00\vhpl00.vho

.....................................\...\....\.....\vhpl01.vho

.....................................\_ngo\netlist.lst

.....................................\.xmsgs\map.xmsgs

.....................................\......\ngdbuild.xmsgs

.....................................\......\par.xmsgs

.....................................\......\pn_parser.xmsgs

.....................................\......\trce.xmsgs

.....................................\......\xst.xmsgs

.....................................\xst\dump.xst\adder.prj\ngx\notopt

.....................................\...\........\.........\...\opt

.....................................\...\........\.........\ngx

.....................................\...\........\adder.prj

.....................................\...\work\sub00

.....................................\isim\temp

.....................................\xst\dump.xst

.....................................\...\projnav.tmp

.....................................\...\work

.....................................\ipcore_dir

.....................................\iseconfig

.....................................\isim

.....................................\xlnx_auto_0_xdb

.....................................\xst

.....................................\_ngo

.....................................\_xmsgs

VHDL Design of 31-bit Pipelined Adder

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