文件名称:rs232_syscon

  • 所属分类:
  • 汇编语言
  • 资源属性:
  • [C/C++] [源码]
  • 上传时间:
  • 2016-05-20
  • 文件大小:
  • 760kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • r***
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core RS232

core digital-core RS232

core digital




(系统自动生成,下载前可以参看下载内容)

下载文件列表





rs232_syscon\tags\V001\b13c_environment.zip

............\....\....\rs232_syscon.doc

............\....\....\rs232_syscon.v

............\.runk\b13c_environment\auto_baud_with_tracking.v

............\.....\................\bugcheck1.C

............\.....\................\bugche~1.232

............\.....\................\BUGCHE~1.HEX

............\.....\................\BUGCHE~1.LST

............\.....\................\BUGCHE~1.SYM

............\.....\................\pndkr_1e.ucf

............\.....\................\README.txt

............\.....\................\reg_8_iorw_clrset.v

............\.....\................\reg_8_io_clrset.v

............\.....\................\risc16f84_clk2x.v

............\.....\................\rs232_syscon.v

............\.....\................\serial.v

............\.....\................\srec_to_rs232.pl

............\.....\................\top.v

............\.....\................\vga_128_by_92.v

............\.....\................\xilinx_block_ram_3_3.v

............\.....\................\xilinx_block_ram_8_16.v

............\.....\b13c_environment.zip

............\.....\rs232_syscon.doc

............\.....\rs232_syscon.v

............\.....\source_rs232_syscon_showcase_VHDL\auto_baud_pack.vhd

............\.....\.................................\baud_mod_pack.vhd

............\.....\.................................\block_ram_pack.vhd

............\.....\.................................\bram_18bit.txt

............\.....\.................................\brevia_board.lpf

............\.....\.................................\brevia_board_no_sram.lpf

............\.....\.................................\bus_arbiter_pack.vhd

............\.....\.................................\convert_pack.vhd

............\.....\.................................\dds_pack.vhd

............\.....\.................................\fifo_pack.vhd

............\.....\.................................\fpga.vhd

............\.....\.................................\fpga_orig.vhd

............\.....\.................................\pingpong_pack.vhd

............\.....\.................................\rs232_syscon_pack.vhd

............\.....\.................................\sine_lut_5000_x_16.vhd

............\.....\.................................\testbench\pull_pack_sim.vhd

............\.....\.................................\.........\rs232_test_in.txt

............\.....\.................................\.........\rs232_test_out.txt

............\.....\.................................\.........\testbench.vhd

............\.....\.................................\.........\translator_wave.do

............\.....\.................................\.........\uart_ascii_control_port_sim.vhd

............\.....\.................................\.........\wave.do

............\.....\.................................\txt_util.vhd

............\.....\.................................\uart_sqclk_pack.vhd

............\.....\source_rs232_syscon_showcase_VHDL.zip

............\web_uploads\b10_safe_12_18_01_dual_path.zip

............\...........\b11_risc16f84_05_03_02.zip

............\...........\b13_safe_09_17_02.zip

............\...........\documentation.shtml

............\...........\download.shtml

............\...........\Image4.gif

............\...........\index.shtml

............\...........\people.shtml

............\...........\rs232_syscon.htm

............\...........\rs232_syscon.pdf

............\...........\rs232_syscon1.doc

............\...........\rs232_syscon_1_00_source.zip

............\...........\rs232_syscon_1_01_xsoc.zip

............\...........\rs232_syscon_autobaud.zip

............\...........\rs232_syscon_soc1.zip

............\...........\rs232_syscon_soc2.zip

............\...........\rs232_syscon_soc3.zip

............\...........\srec_to_rs232.pl

............\trunk\source_rs232_syscon_showcase_VHDL\testbench

............\.ags\V001

............\.runk\b13c_environment

............\.....\source_rs232_syscon_showcase_VHDL

............\branches

............\tags

............\trunk

............\web_uploads

rs232_syscon

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