文件名称:project_1
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使用fpga实现mips处理器代码verilog-Use Code verilog fpga realize mips processor
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下载文件列表
project_1\project_1.cache\wt\java_command_handlers.wdf
.........\...............\..\synthesis.wdf
.........\...............\..\webtalk_pa.xml
.........\..........ioplanning\constrs_1\designprops.xml
.........\....................\.........\usercols.xml
.........\..........runs\.jobs\vrs_config_1.xml
.........\..............\.....\vrs_config_10.xml
.........\..............\.....\vrs_config_11.xml
.........\..............\.....\vrs_config_12.xml
.........\..............\.....\vrs_config_13.xml
.........\..............\.....\vrs_config_14.xml
.........\..............\.....\vrs_config_15.xml
.........\..............\.....\vrs_config_16.xml
.........\..............\.....\vrs_config_17.xml
.........\..............\.....\vrs_config_18.xml
.........\..............\.....\vrs_config_19.xml
.........\..............\.....\vrs_config_2.xml
.........\..............\.....\vrs_config_20.xml
.........\..............\.....\vrs_config_21.xml
.........\..............\.....\vrs_config_22.xml
.........\..............\.....\vrs_config_23.xml
.........\..............\.....\vrs_config_24.xml
.........\..............\.....\vrs_config_25.xml
.........\..............\.....\vrs_config_26.xml
.........\..............\.....\vrs_config_27.xml
.........\..............\.....\vrs_config_28.xml
.........\..............\.....\vrs_config_29.xml
.........\..............\.....\vrs_config_3.xml
.........\..............\.....\vrs_config_30.xml
.........\..............\.....\vrs_config_31.xml
.........\..............\.....\vrs_config_32.xml
.........\..............\.....\vrs_config_33.xml
.........\..............\.....\vrs_config_34.xml
.........\..............\.....\vrs_config_35.xml
.........\..............\.....\vrs_config_36.xml
.........\..............\.....\vrs_config_37.xml
.........\..............\.....\vrs_config_38.xml
.........\..............\.....\vrs_config_39.xml
.........\..............\.....\vrs_config_4.xml
.........\..............\.....\vrs_config_40.xml
.........\..............\.....\vrs_config_41.xml
.........\..............\.....\vrs_config_42.xml
.........\..............\.....\vrs_config_5.xml
.........\..............\.....\vrs_config_6.xml
.........\..............\.....\vrs_config_7.xml
.........\..............\.....\vrs_config_8.xml
.........\..............\.....\vrs_config_9.xml
.........\..............\impl_1\.init_design.begin.rst
.........\..............\......\.init_design.end.rst
.........\..............\......\.opt_design.begin.rst
.........\..............\......\.opt_design.end.rst
.........\..............\......\.place_design.begin.rst
.........\..............\......\.place_design.end.rst
.........\..............\......\.route_design.begin.rst
.........\..............\......\.route_design.end.rst
.........\..............\......\.Vivado Implementation.queue.rst
.........\..............\......\.vivado.begin.rst
.........\..............\......\.vivado.end.rst
.........\..............\......\.write_bitstream.begin.rst
.........\..............\......\.write_bitstream.end.rst
.........\..............\......\gen_run.xml
.........\..............\......\htr.txt
.........\..............\......\init_design.pb
.........\..............\......\ISEWrap.js
.........\..............\......\ISEWrap.sh
.........\..............\......\mipsfpga_nexys4.bit
.........\..............\......\mipsfpga_nexys4.dcp
.........\..............\......\mipsfpga_nexys4.tcl
.........\..............\......\mipsfpga_nexys4.vdi
.........\..............\......\mipsfpga_nexys4_11200.backup.vdi
.........\..............\......\mipsfpga_nexys4_clock_utilization_placed.rpt
.........\..............\......\mipsfpga_nexys4_control_sets_placed.rpt
.........\..............\......\mipsfpga_nexys4_drc_routed.pb
.........\..............\......\mipsfpga_nexys4_drc_routed.rpt
.........\..............\......\mipsfpga_nexys4_io_placed.rpt
.........\..............\......\mipsfpga_nexys4_opt.dcp
.........\..............\......\mipsfpga_nexys4_placed.dcp
.........\..............\......\mipsfpga_nexys4_power_routed.rpt
.........\..............\......\mipsfpga_nexys4_power_summary_routed.pb