文件名称:cpu2
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实现简单的CPU系统，包括ALU,MAR,MBR,PC,IR,CU,BR等模块，可以实现简单的指令，如加减乘，逻辑/循环移位，与或非等-Achieve a simple CPU system, including the ALU, MAR, MBR, PC, IR, CU, BR and other modules, you can achieve a simple instruction, such as addition and subtraction multiplication, logical/cyclic shift, and the like or
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下载文件列表
cpu2
....\.Xil
....\ALU.cmd_log
....\ALU.lso
....\ALU.prj
....\ALU.syr
....\ALU.vhd
....\ALU.xst
....\ALU_envsettings.html
....\ALU_summary.html
....\ALU_xst.xrpt
....\BR.vhd
....\cpu2.gise
....\cpu2.xise
....\CU.vhd
....\Display.vhd
....\fuse.log
....\fuse.xmsgs
....\fuseRelaunch.cmd
....\impact.xsl
....\impact_impact.xwbt
....\Instruction
....\...........\1+..+100
....\...........\........\memory1.coe
....\...........\Multiplex
....\...........\.........\multiplex.txt
....\...........\shift
....\...........\.....\shift.coe
....\...........\.....\shift.txt
....\...........\第一题
....\...........\......\memory.coe
....\...........\第三题
....\...........\......\memory.coe
....\...........\第二题
....\...........\......\memory.coe
....\ipcore_dir
....\..........\coregen.cgp
....\..........\coregen.log
....\..........\create_memory.tcl
....\..........\edit_memory.tcl
....\..........\memory
....\..........\memory.asy
....\..........\memory.gise
....\..........\memory.mif
....\..........\memory.ncf
....\..........\memory.ngc
....\..........\memory.sym
....\..........\memory.vhd
....\..........\memory.vho
....\..........\memory.xco
....\..........\memory.xise
....\..........\......\blk_mem_gen_v7_3_readme.txt
....\..........\......\doc
....\..........\......\...\blk_mem_gen_v7_3_vinfo.html
....\..........\......\...\pg058-blk-mem-gen.pdf
....\..........\......\example_design
....\..........\......\..............\memory_exdes.ucf
....\..........\......\..............\memory_exdes.vhd
....\..........\......\..............\memory_exdes.xdc
....\..........\......\..............\memory_prod.vhd
....\..........\......\implement
....\..........\......\.........\implement.bat
....\..........\......\.........\implement.sh
....\..........\......\.........\planAhead_ise.bat
....\..........\......\.........\planAhead_ise.sh
....\..........\......\.........\planAhead_ise.tcl
....\..........\......\.........\xst.prj
....\..........\......\.........\xst.scr
....\..........\......\simulation
....\..........\......\..........\addr_gen.vhd
....\..........\......\..........\bmg_stim_gen.vhd
....\..........\......\..........\bmg_tb_pkg.vhd
....\..........\......\..........\checker.vhd
....\..........\......\..........\data_gen.vhd
....\..........\......\..........\functional
....\..........\......\..........\..........\simcmds.tcl
....\..........\......\..........\..........\simulate_isim.bat
....\..........\......\..........\..........\simulate_mti.bat
....\..........\......\..........\..........\simulate_mti.do
....\..........\......\..........\..........\simulate_mti.sh
....\..........\......\..........\..........\simulate_ncsim.sh
....\..........\......\..........\..........\simulate_vcs.sh
....\..........\......\..........\..........\ucli_commands.key
....\..........\......\..........\..........\vcs_session.tcl
....\..........\......\..........\..........\wave_mti.do
....\..........\......\..........\..........\wave_ncsim.sv
....\..........\......\..........\memory_synth.vhd
....\..........\......\..........\memory_tb.vhd
....\..........\......\..........\random.vhd
....\..........\......\..........\timing
....\..........\......\..........\......\simcmds.tcl
....\..........\......\..........\......\simulate_isim.bat
....\..........\......\..........\......\simulate_mti.bat
....\..........\......\..........\......\simulate_mti.do
....\..........\......\..........\......\simulate_mti.sh
....\..........\......\..........\......\simulate_ncsim.sh
....\..........\......\..........\......\simulate_vcs.sh
....\..........\......\..........\......\ucli_commands.key
....\..........\......\..........\......\vcs_session.tcl
....\..........\......\..........\......\wave_mti.do