文件名称:ADDR
介绍说明－－下载内容均来自于网络，请自行研究使用
8位全加器，包括半加器verilog文件，全加器verilog文件，8位全加器verilog文件，和8位全加器测试testbench文件-8 full adder, including half adder, full adder Verilog file, Verilog file, 8 full adder Verilog files, and 8 full adder test testbench file
(系统自动生成,下载前可以参看下载内容)
下载文件列表
ADDR\ADDR.cr.mti
....\ADDR.mpf
....\ADDR.qpf
....\ADDR.qsf
....\ADDR.qws
....\ADDR.v
....\ADDR.v.bak
....\ADDR_TB.v
....\ADDR_TB.v.bak
....\db\ADDR.cbx.xml
....\..\ADDR.cmp.rdb
....\..\ADDR.cmp_merge.kpt
....\..\ADDR.db_info
....\..\ADDR.hier_info
....\..\ADDR.hif
....\..\ADDR.ipinfo
....\..\ADDR.lpc.html
....\..\ADDR.lpc.rdb
....\..\ADDR.lpc.txt
....\..\ADDR.map.ammdb
....\..\ADDR.map.bpm
....\..\ADDR.map.cdb
....\..\ADDR.map.hdb
....\..\ADDR.map.kpt
....\..\ADDR.map.logdb
....\..\ADDR.map.qmsg
....\..\ADDR.map.rdb
....\..\ADDR.map_bb.cdb
....\..\ADDR.map_bb.hdb
....\..\ADDR.map_bb.logdb
....\..\ADDR.pre_map.hdb
....\..\ADDR.pti_db_list.ddb
....\..\ADDR.root_partition.map.reg_db.cdb
....\..\ADDR.rtlv.hdb
....\..\ADDR.rtlv_sg.cdb
....\..\ADDR.rtlv_sg_swap.cdb
....\..\ADDR.sgdiff.cdb
....\..\ADDR.sgdiff.hdb
....\..\ADDR.sld_design_entry.sci
....\..\ADDR.sld_design_entry_dsc.sci
....\..\ADDR.smart_action.txt
....\..\ADDR.sta.qmsg
....\..\ADDR.tis_db_list.ddb
....\..\ADDR.tmw_info
....\..\logic_util_heursitic.dat
....\..\prev_cmp_ADDR.qmsg
....\F_ADDR.v
....\F_ADDR.v.bak
....\H_ADDR.v
....\H_ADDR.v.bak
....\incremental_db\compiled_partitions\ADDR.db_info
....\..............\...................\ADDR.root_partition.map.cdb
....\..............\...................\ADDR.root_partition.map.dpi
....\..............\...................\ADDR.root_partition.map.hbdb.cdb
....\..............\...................\ADDR.root_partition.map.hbdb.hb_info
....\..............\...................\ADDR.root_partition.map.hbdb.hdb
....\..............\...................\ADDR.root_partition.map.hbdb.sig
....\..............\...................\ADDR.root_partition.map.hdb
....\..............\...................\ADDR.root_partition.map.kpt
....\..............\README
....\output_files\ADDR.done
....\............\ADDR.flow.rpt
....\............\ADDR.map.rpt
....\............\ADDR.map.summary
....\vsim.wlf
....\work\@a@d@d@r\verilog.prw
....\....\........\verilog.psm
....\....\........\_primary.dat
....\....\........\_primary.dbs
....\....\........\_primary.vhd
....\....\........_@t@b\verilog.prw
....\....\.............\verilog.psm
....\....\.............\_primary.dat
....\....\.............\_primary.dbs
....\....\.............\_primary.vhd
....\....\.f_@a@d@d@r\verilog.prw
....\....\...........\verilog.psm
....\....\...........\_primary.dat
....\....\...........\_primary.dbs
....\....\...........\_primary.vhd
....\....\.h_@a@d@d@r\verilog.prw
....\....\...........\verilog.psm
....\....\...........\_primary.dat
....\....\...........\_primary.dbs
....\....\...........\_primary.vhd
....\....\_info
....\....\_vmake
....\incremental_db\compiled_partitions
....\work\@a@d@d@r
....\....\@a@d@d@r_@t@b
....\....\@f_@a@d@d@r
....\....\@h_@a@d@d@r
....\....\_temp
....\db
....\incremental_db
....\output_files
....\work
ADDR