文件名称:udp_send1
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基于FPGA的UDP硬件协议栈， 全部用SystemVerilog写的，不需CPU参与，包括独立的MAC模块。 支持外部phy的配置，支持GMII和RGMII模式。 以下是接口
input clk50,
input rst_n,
///////////////////////
//interface to user module
input [7:0] wr_data,
input wr_clk,
input wr_en,
output wr_full,
output [7:0] rd_data,
input rd_clk,
input rd_en,
output rd_empty,
input [31:0] local_ipaddr, //FPGA ip address
input [31:0] remote_ipaddr, //PC ip address
input [15:0] local_port, //FPGA port number
//interface to ethernet phy
output mdc,
inout mdio,
output phy_rst_n,
output is_link_up,
`ifdef RGMII_IF
input [3:0] rx_data,
output logic [3:0] tx_data,
`else
input [7:0] rx_data,
output logic [7:0] tx_data,
`endif
input rx_clk,
input rx_data_valid,
input gtx_clk,
output logic tx_en-UDP hardware stack, written in system verilog, do nt need CPU.Projgect includes MAC Layer,support phy configuration.support gmii and rgmii mode. the interface is as the follows:
input clk50,
input rst_n,
///////////////////////
//interface to user module
input [7:0] wr_data,
input wr_clk,
input wr_en,
output wr_full,
output [7:0] rd_data,
input rd_clk,
input rd_en,
output rd_empty,
input [31:0] local_ipaddr, //FPGA ip address
input [31:0] remote_ipaddr, //PC ip address
input [15:0] local_port, //FPGA port number
//interface to ethernet phy
output mdc,
inout mdio,
output phy_rst_n,
output is_link_up,
`ifdef RGMII_IF
input [3:0] rx_data,
output logic [3:0] tx_data,
`else
input [7:0] rx_data,
output logic [7:0] tx_data,
`endif
input rx_clk,
input rx_data
input clk50,
input rst_n,
///////////////////////
//interface to user module
input [7:0] wr_data,
input wr_clk,
input wr_en,
output wr_full,
output [7:0] rd_data,
input rd_clk,
input rd_en,
output rd_empty,
input [31:0] local_ipaddr, //FPGA ip address
input [31:0] remote_ipaddr, //PC ip address
input [15:0] local_port, //FPGA port number
//interface to ethernet phy
output mdc,
inout mdio,
output phy_rst_n,
output is_link_up,
`ifdef RGMII_IF
input [3:0] rx_data,
output logic [3:0] tx_data,
`else
input [7:0] rx_data,
output logic [7:0] tx_data,
`endif
input rx_clk,
input rx_data_valid,
input gtx_clk,
output logic tx_en-UDP hardware stack, written in system verilog, do nt need CPU.Projgect includes MAC Layer,support phy configuration.support gmii and rgmii mode. the interface is as the follows:
input clk50,
input rst_n,
///////////////////////
//interface to user module
input [7:0] wr_data,
input wr_clk,
input wr_en,
output wr_full,
output [7:0] rd_data,
input rd_clk,
input rd_en,
output rd_empty,
input [31:0] local_ipaddr, //FPGA ip address
input [31:0] remote_ipaddr, //PC ip address
input [15:0] local_port, //FPGA port number
//interface to ethernet phy
output mdc,
inout mdio,
output phy_rst_n,
output is_link_up,
`ifdef RGMII_IF
input [3:0] rx_data,
output logic [3:0] tx_data,
`else
input [7:0] rx_data,
output logic [7:0] tx_data,
`endif
input rx_clk,
input rx_data
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下载文件列表
udp_send
........\src
........\...\data_gen.sv
........\...\data_source.sv
........\...\dp_ram.v
........\...\eth_fsm.sv
........\...\headers_ram.v
........\...\icmp_ram_int.v
........\...\mac_config.sv
........\...\mac_rx_path.sv
........\...\mac_tx_path.sv
........\...\rst_ctrl.v
........\...\rx_ram.sv
........\...\rx_ram_int.v
........\...\simple_mac
........\...\..........\CRC32_D8_AAL5.v
........\...\..........\CRC32_D8_TX.v
........\...\..........\mac_fifo_rx.v
........\...\..........\mac_fifo_rx_size.v
........\...\..........\mac_fifo_tx.v
........\...\..........\mac_fifo_tx_size.v
........\...\..........\rx_header_align32.sv
........\...\..........\simple_mac_bus_arb.sv
........\...\..........\simple_mac_phy_mdio.sv
........\...\..........\simple_mac_regs.sv
........\...\..........\simple_mac_rx_gmii.sv
........\...\..........\simple_mac_rx_path.sv
........\...\..........\simple_mac_rx_rgmii.sv
........\...\..........\simple_mac_top.sv
........\...\..........\simple_mac_tx_gmii.sv
........\...\..........\simple_mac_tx_path.sv
........\...\..........\simple_mac_tx_rgmii.sv
........\...\..........\tx_header_align32.sv
........\...\tcpip_hw.sv
........\...\tcpip_hw1.sv
........\...\tcpip_hw_defines.sv
........\...\tcpip_hw_ifs.sv
........\...\tcpip_hw_top.v
........\...\tcpip_hw_top.v.1
........\...\tcp_send.sdc
........\...\tx_ram.sv
........\...\tx_ram_int.v
........\...\type_defs.pkg.sv
........\...\vendor
........\...\......\altera
........\...\......\......\sync_fifo.v
........\...\......\......\sync_fifo_bb.v
........\tcpip_hw.qpf
........\tcpip_hw.qsf