文件名称:wiznet5500_Verilog
介绍说明－－下载内容均来自于网络，请自行研究使用
使用Xilinx Spartan-6 XC6SLX9的FPGA驱动Wiznet5500网卡芯片的Verilog设计，可以发送和接收，已经测试，无误。-Using the Xilinx Spartan-6 XC6SLX9 FPGA driver The Wiznet5500 network card chip Verilog design can be sent and received, has been tested, and is correct.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
.gitignore
LICENSE
Mojo-Base.xise
iseconfig
.........\Mojo-Base.projectmgr
.........\mojo_top.xreport
src
...\fifo.v
...\mojo.ucf
...\mojo_top.v
...\wiznet5500.v
...\wiznet5500_parameters.v
syn
...\Mojo-Base.gise
...\_ngo
...\....\netlist.lst
...\_xmsgs
...\......\bitgen.xmsgs
...\......\map.xmsgs
...\......\ngdbuild.xmsgs
...\......\par.xmsgs
...\......\pn_parser.xmsgs
...\......\trce.xmsgs
...\......\xst.xmsgs
...\mojo_top.bgn
...\mojo_top.bin
...\mojo_top.bit
...\mojo_top.bld
...\mojo_top.cmd_log
...\mojo_top.drc
...\mojo_top.lso
...\mojo_top.ncd
...\mojo_top.ngc
...\mojo_top.ngd
...\mojo_top.ngr
...\mojo_top.pad
...\mojo_top.par
...\mojo_top.pcf
...\mojo_top.prj
...\mojo_top.ptwx
...\mojo_top.stx
...\mojo_top.syr
...\mojo_top.twr
...\mojo_top.twx
...\mojo_top.unroutes
...\mojo_top.ut
...\mojo_top.xpi
...\mojo_top.xst
...\mojo_top_bitgen.xwbt
...\mojo_top_envsettings.html
...\mojo_top_guide.ncd
...\mojo_top_map.map
...\mojo_top_map.mrp
...\mojo_top_map.ncd
...\mojo_top_map.ngm
...\mojo_top_map.xrpt
...\mojo_top_ngdbuild.xrpt
...\mojo_top_pad.csv
...\mojo_top_pad.txt
...\mojo_top_par.xrpt
...\mojo_top_summary.html
...\mojo_top_summary.xml
...\mojo_top_usage.xml
...\mojo_top_xst.xrpt
...\par_usage_statistics.html
...\usage_statistics_webtalk.html
...\webtalk.log
...\webtalk_pn.xml
...\xlnx_auto_0_xdb
...\...............\cst.xbcd
...\xst
...\...\dump.xst
...\...\........\mojo_top.prj
...\...\projnav.tmp
...\...\work
...\...\....\work.sdbl
...\...\....\work.sdbx