文件名称:class11_uart_tx
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verilog编写的串口发送程序，学习串口的话可以用作参考，已经实际验证过-Verilog prepared by the serial port to send procedures, learning serial port can be used as a reference, has actually verified
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下载文件列表
class11_uart_tx\doc\UART串口发送模块设计.docx
...............\...\uart发送模块设计.vsdx
...............\prj\db\logic_util_heursitic.dat
...............\...\..\uart_byte_tx.autoh_e40e1.map.reg_db.cdb
...............\...\..\uart_byte_tx.cbx.xml
...............\...\..\uart_byte_tx.cmp.rdb
...............\...\..\uart_byte_tx.cmp_merge.kpt
...............\...\..\uart_byte_tx.db_info
...............\...\..\uart_byte_tx.hier_info
...............\...\..\uart_byte_tx.hif
...............\...\..\uart_byte_tx.ipinfo
...............\...\..\uart_byte_tx.lpc.html
...............\...\..\uart_byte_tx.lpc.rdb
...............\...\..\uart_byte_tx.lpc.txt
...............\...\..\uart_byte_tx.map.ammdb
...............\...\..\uart_byte_tx.map.bpm
...............\...\..\uart_byte_tx.map.cdb
...............\...\..\uart_byte_tx.map.hdb
...............\...\..\uart_byte_tx.map.kpt
...............\...\..\uart_byte_tx.map.logdb
...............\...\..\uart_byte_tx.map.qmsg
...............\...\..\uart_byte_tx.map.rdb
...............\...\..\uart_byte_tx.map_bb.cdb
...............\...\..\uart_byte_tx.map_bb.hdb
...............\...\..\uart_byte_tx.map_bb.logdb
...............\...\..\uart_byte_tx.pre_map.hdb
...............\...\..\uart_byte_tx.pti_db_list.ddb
...............\...\..\uart_byte_tx.root_partition.map.reg_db.cdb
...............\...\..\uart_byte_tx.rtlv.hdb
...............\...\..\uart_byte_tx.rtlv_sg.cdb
...............\...\..\uart_byte_tx.rtlv_sg_swap.cdb
...............\...\..\uart_byte_tx.sgdiff.cdb
...............\...\..\uart_byte_tx.sgdiff.hdb
...............\...\..\uart_byte_tx.sld_design_entry.sci
...............\...\..\uart_byte_tx.sld_design_entry_dsc.sci
...............\...\..\uart_byte_tx.smart_action.txt
...............\...\..\uart_byte_tx.smp_dump.txt
...............\...\..\uart_byte_tx.syn_hier_info
...............\...\..\uart_byte_tx.tis_db_list.ddb
...............\...\..\uart_byte_tx.tmw_info
...............\...\incremental_db\compiled_partitions\uart_byte_tx.autoh_e40e1.map.cdb
...............\...\..............\...................\uart_byte_tx.autoh_e40e1.map.dpi
...............\...\..............\...................\uart_byte_tx.autoh_e40e1.map.hdb
...............\...\..............\...................\uart_byte_tx.autoh_e40e1.map.kpt
...............\...\..............\...................\uart_byte_tx.autoh_e40e1.map.logdb
...............\...\..............\...................\uart_byte_tx.db_info
...............\...\..............\...................\uart_byte_tx.root_partition.map.cdb
...............\...\..............\...................\uart_byte_tx.root_partition.map.dpi
...............\...\..............\...................\uart_byte_tx.root_partition.map.hbdb.cdb
...............\...\..............\...................\uart_byte_tx.root_partition.map.hbdb.hb_info
...............\...\..............\...................\uart_byte_tx.root_partition.map.hbdb.hdb
...............\...\..............\...................\uart_byte_tx.root_partition.map.hbdb.sig
...............\...\..............\...................\uart_byte_tx.root_partition.map.hdb
...............\...\..............\...................\uart_byte_tx.root_partition.map.kpt
...............\...\..............\README
...............\...\.p\greybox_tmp\cbx_args.txt
...............\...\..\issp.qip
...............\...\..\issp.v
...............\...\..\issp_bb.v
...............\...\output_files\uart_byte_tx.done
...............\...\............\uart_byte_tx.fit.smsg
...............\...\............\uart_byte_tx.fit.summary
...............\...\............\uart_byte_tx.flow.rpt
...............\...\............\uart_byte_tx.jdi
...............\...\............\uart_byte_tx.map.rpt
...............\...\............\uart_byte_tx.map.summary
...............\...\............\uart_byte_tx.pin
...............\...\............\uart_byte_tx.sof
...............\...\............\uart_byte_tx.sta.summary
...............\...\simulation\modelsim\modelsim.ini
...............\...\..........\........\msim_transcript
...............\...\..........\........\rtl_work\issp\verilog.prw
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