文件名称:pwm_led
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呼吸灯显示的一个效果是，灯从灭缓慢的变亮，然后从亮缓慢的变暗，如此循环。
在刚开始设计呼吸灯的时候，可能大家想通过LED灯两端的电压，使电压从零逐渐的增加来实现从灭变亮的这个过程，然后再将电压逐渐降低到零来实现从亮到灭。但是咱们必须要明白一个事实，FPGA引脚输出的电压只有“0”和“1”之分，我们是不能使FPGA的引脚输出电压慢慢增加的。所以通过控制LED灯两端的电压来实现呼吸灯是达不到效果的。
虽然咱们不能使FPGA引脚输出电压从逐渐增加或减小，但是我们可以控制其输出高低电平的时间，若要控制呼吸灯从灭到亮的过程，我们可以使呼吸灯在单位时间内亮的时间依次增加，这样就可以形成这种逐渐变亮的效果。-One effect of the breathable lamp display is that the light fades slowly and then slowly darkens the light, so the loop.
At the beginning of the design of the breathing light, you may want to LED voltage at both ends of the voltage zero to gradually increase the light to achieve this process, and then gradually reduce the voltage to zero to achieve light to off The But we have to understand the fact that the FPGA pin output voltage is only 0 and 1 of the points, we can not make the FPGA pin output voltage slowly increased. So by controlling the voltage across the LED lights to achieve the effect of breathing lights is not up to the effect.
Although we can not make the FPGA pin output voltage gradually increase or decrease, but we can control the output of its high and low time, to control the breathing light the light to the process of light, we can make the breathing light in the unit time Of the time in turn increase, so that you can form this gradually brightening eff
在刚开始设计呼吸灯的时候，可能大家想通过LED灯两端的电压，使电压从零逐渐的增加来实现从灭变亮的这个过程，然后再将电压逐渐降低到零来实现从亮到灭。但是咱们必须要明白一个事实，FPGA引脚输出的电压只有“0”和“1”之分，我们是不能使FPGA的引脚输出电压慢慢增加的。所以通过控制LED灯两端的电压来实现呼吸灯是达不到效果的。
虽然咱们不能使FPGA引脚输出电压从逐渐增加或减小，但是我们可以控制其输出高低电平的时间，若要控制呼吸灯从灭到亮的过程，我们可以使呼吸灯在单位时间内亮的时间依次增加，这样就可以形成这种逐渐变亮的效果。-One effect of the breathable lamp display is that the light fades slowly and then slowly darkens the light, so the loop.
At the beginning of the design of the breathing light, you may want to LED voltage at both ends of the voltage zero to gradually increase the light to achieve this process, and then gradually reduce the voltage to zero to achieve light to off The But we have to understand the fact that the FPGA pin output voltage is only 0 and 1 of the points, we can not make the FPGA pin output voltage slowly increased. So by controlling the voltage across the LED lights to achieve the effect of breathing lights is not up to the effect.
Although we can not make the FPGA pin output voltage gradually increase or decrease, but we can control the output of its high and low time, to control the breathing light the light to the process of light, we can make the breathing light in the unit time Of the time in turn increase, so that you can form this gradually brightening eff
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下载文件列表
pwm_led
.......\design
.......\......\pwm_led.v
.......\doc
.......\...\pwm_sim.png
.......\pin.txt
.......\quartus_prj
.......\...........\db
.......\...........\..\.cmp.kpt
.......\...........\..\prev_cmp_pwm_led.qmsg
.......\...........\..\pwm_led.db_info
.......\...........\..\pwm_led.sld_design_entry.sci
.......\...........\incremental_db
.......\...........\..............\compiled_partitions
.......\...........\..............\...................\pwm_led.db_info
.......\...........\..............\README
.......\...........\output_files
.......\...........\............\Chain_1.cdf
.......\...........\............\Chain_final.cdf
.......\...........\............\pwm_led.asm.rpt
.......\...........\............\pwm_led.done
.......\...........\............\pwm_led.fit.rpt
.......\...........\............\pwm_led.fit.smsg
.......\...........\............\pwm_led.fit.summary
.......\...........\............\pwm_led.flow.rpt
.......\...........\............\pwm_led.jdi
.......\...........\............\pwm_led.map.rpt
.......\...........\............\pwm_led.map.summary
.......\...........\............\pwm_led.pin
.......\...........\............\pwm_led.sof
.......\...........\pwm_led.qpf
.......\...........\pwm_led.qsf
.......\...........\pwm_led.qsf.bak
.......\...........\pwm_led.qws
.......\sim
.......\...\aaa.cr.mti
.......\...\aaa.mpf
.......\...\tb_pwm_led.v
.......\...\vsim.wlf
.......\...\work
.......\...\....\pwm_led
.......\...\....\.......\verilog.prw
.......\...\....\.......\verilog.psm
.......\...\....\.......\_primary.dat
.......\...\....\.......\_primary.dbs
.......\...\....\.......\_primary.vhd
.......\...\....\tb_pwm_led
.......\...\....\..........\verilog.prw
.......\...\....\..........\verilog.psm
.......\...\....\..........\_primary.dat
.......\...\....\..........\_primary.dbs
.......\...\....\..........\_primary.vhd
.......\...\....\_info
.......\...\....\_temp
.......\...\....\.....\vlog3h05j7
.......\...\....\.....\vlog4qvswk
.......\...\....\.....\vlog54st9n
.......\...\....\.....\vlogb5w9k2
.......\...\....\.....\vlogffyhf4
.......\...\....\.....\vlogni2c1b
.......\...\....\.....\vlogshv1cd
.......\...\....\.....\vlogt730rx
.......\...\....\.....\vlogy4vvm1
.......\...\....\_vmake