文件名称:DDR_TEST

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  • VHDL编程
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  • [PDF]
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  • 2017-02-25
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  • 6.58mb
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基于xc65slx16的ise 14.7 DDR3测试模版,经过验证,可供fpga开发参考学习,也可作为开发模版。-Based on xc65slx16 ise 14.7 DDR3 test template, validated and can be used for reference in the fpga development study, also can be used as a template development.
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下载文件列表





DDR_TEST\MIG_PRG\DOC\SPARTAN6 MCB MIG Core生成.doc

........\.......\...\ug388.pdf

........\.......\...\ug416.pdf

........\.......\MIG_RPG\mig.prj

........\.......\.......\..s603\docs\ug388.pdf

........\.......\.......\......\....\ug416.pdf

........\.......\.......\......\example_design\datasheet.txt

........\.......\.......\......\..............\log.txt

........\.......\.......\......\..............\mig.prj

........\.......\.......\......\..............\par\create_ise.bat

........\.......\.......\......\..............\...\example_top.ucf

........\.......\.......\......\..............\...\icon_coregen.xco

........\.......\.......\......\..............\...\ila_coregen.xco

........\.......\.......\......\..............\...\ise_flow.bat

........\.......\.......\......\..............\...\ise_run.txt

........\.......\.......\......\..............\...\makeproj.bat

........\.......\.......\......\..............\...\mem_interface_top.ut

........\.......\.......\......\..............\...\readme.txt

........\.......\.......\......\..............\...\rem_files.bat

........\.......\.......\......\..............\...\set_ise_prop.tcl

........\.......\.......\......\..............\...\vio_coregen.xco

........\.......\.......\......\..............\rtl\example_top.v

........\.......\.......\......\..............\...\infrastructure.v

........\.......\.......\......\..............\...\mcb_controller\iodrp_controller.v

........\.......\.......\......\..............\...\..............\iodrp_mcb_controller.v

........\.......\.......\......\..............\...\..............\mcb_raw_wrapper.v

........\.......\.......\......\..............\...\..............\mcb_soft_calibration.v

........\.......\.......\......\..............\...\..............\mcb_soft_calibration_top.v

........\.......\.......\......\..............\...\..............\mcb_ui_top.v

........\.......\.......\......\..............\...\memc_tb_top.v

........\.......\.......\......\..............\...\memc_wrapper.v

........\.......\.......\......\..............\...\traffic_gen\afifo.v

........\.......\.......\......\..............\...\...........\cmd_gen.v

........\.......\.......\......\..............\...\...........\cmd_prbs_gen.v

........\.......\.......\......\..............\...\...........\data_prbs_gen.v

........\.......\.......\......\..............\...\...........\init_mem_pattern_ctr.v

........\.......\.......\......\..............\...\...........\mcb_flow_control.v

........\.......\.......\......\..............\...\...........\mcb_traffic_gen.v

........\.......\.......\......\..............\...\...........\rd_data_gen.v

........\.......\.......\......\..............\...\...........\read_data_path.v

........\.......\.......\......\..............\...\...........\read_posted_fifo.v

........\.......\.......\......\..............\...\...........\sp6_data_gen.v

........\.......\.......\......\..............\...\...........\tg_status.v

........\.......\.......\......\..............\...\...........\v6_data_gen.v

........\.......\.......\......\..............\...\...........\write_data_path.v

........\.......\.......\......\..............\...\...........\wr_data_gen.v

........\.......\.......\......\..............\sim\functional\ddr3_model_c3.v

........\.......\.......\......\..............\...\..........\ddr3_model_parameters_c3.vh

........\.......\.......\......\..............\...\..........\isim.bat

........\.......\.......\......\..............\...\..........\isim.tcl

........\.......\.......\......\..............\...\..........\mis603.prj

........\.......\.......\......\..............\...\..........\readme.txt

........\.......\.......\......\..............\...\..........\sim.do

........\.......\.......\......\..............\...\..........\sim_tb_top.v

........\.......\.......\......\..............\.ynth\example_top.lso

........\.......\.......\......\..............\.....\example_top.prj

........\.......\.......\......\..............\.....\mem_interface_top_synp.sdc

........\.......\.......\......\..............\.....\script_synp.tcl

........\.......\.......\......\user_desi

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