文件名称:DDS
介绍说明－－下载内容均来自于网络，请自行研究使用
基于FPGA，Verilog语言编写的DDS信号发生器，可生成方波、正玄波，三角波。-Based FPGA, Verilog language DDS signal generator that generates a square wave, sine wave, triangle wave.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
DDS
...\DDS
...\...\1024.mif
...\...\512.mif
...\...\DDSFPGA.asm.rpt
...\...\DDSFPGA.bdf
...\...\DDSFPGA.done
...\...\DDSFPGA.fit.eqn
...\...\DDSFPGA.fit.rpt
...\...\DDSFPGA.fit.summary
...\...\DDSFPGA.flow.rpt
...\...\DDSFPGA.map.eqn
...\...\DDSFPGA.map.rpt
...\...\DDSFPGA.map.summary
...\...\DDSFPGA.pin
...\...\DDSFPGA.pof
...\...\DDSFPGA.qpf
...\...\DDSFPGA.qsf
...\...\DDSFPGA.qws
...\...\DDSFPGA.sim.rpt
...\...\DDSFPGA.sof
...\...\DDSFPGA.tan.rpt
...\...\DDSFPGA.tan.summary
...\...\DDSFPGA.vwf
...\...\DDSFPGA_assignment_defaults.qdf
...\...\Key.bsf
...\...\clock_d2.bsf
...\...\clock_d2.v
...\...\cmp_state.ini
...\...\control.bsf
...\...\control.v
...\...\control.v.bak
...\...\creat.c
...\...\creat.exe
...\...\datachoose.bsf
...\...\datachoose.v
...\...\db
...\...\..\DDSFPGA.db_info
...\...\..\DDSFPGA.eco.cdb
...\...\..\DDSFPGA.sld_design_entry.sci
...\...\..\DDSFPGA_cmp.qrpt
...\...\..\DDSFPGA_sim.qrpt
...\...\..\altsyncram_88s.tdf
...\...\key.v
...\...\romlookup.bsf
...\...\romlookup.v
...\...\romlookup_bb.v
...\...\squwave.bsf
...\...\squwave.v
...\...\squwave.v.bak
...\...\triawave.bsf
...\...\triawave.v
...\...\triawave.v.bak