文件名称:FPGA_Projects_100

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [Windows] [程序]
  • 上传时间:
  • 2017-02-08
  • 文件大小:
  • 12.81mb
  • 下载次数:
  • 0次
  • 提 供 者:
  • 张*
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

FPGA_Projects_100,例程100例经典程序-FPGA examples
(系统自动生成,下载前可以参看下载内容)

下载文件列表

文件名大小更新时间


100 Power Tips for FPGA Designers - Stavinov Evgeni\100 Power Tips for FPGA Designers - Stavinov Evgeni.mobi
....................................................\FBReaderSetup-0.12.10.exe
....................................................\readme.txt
....................................................\src_book\13.14.15.coding\rtl\coding_style.v
....................................................\........\...............\...\simple.v
....................................................\........\...............\...\synth_support.v
....................................................\........\...............\...\tb.v
....................................................\........\...............\synth\isim.cmd
....................................................\........\...............\.....\sim1.wcfg
....................................................\........\...............\.....\sim2.wcfg
....................................................\........\...............\.....\synth.xise
....................................................\........\...............\.....\synth_support.lso
....................................................\........\.6.inference\rtl\inference.v
....................................................\........\............\synth\inference.lso
....................................................\........\............\.....\inference.ptwx
....................................................\........\............\.....\inference.stx
....................................................\........\............\.....\inference.unroutes
....................................................\........\............\.....\inference.xpi
....................................................\........\............\.....\inference_map.mrp
....................................................\........\............\.....\netgen\map\inference_map.sdf
....................................................\........\............\.....\......\...\inference_map.v
....................................................\........\............\.....\......\synthesis\inference_synthesis.v
....................................................\........\............\.....\synth.xise
....................................................\........\.7.mixed_verilog_vhdl\rtl\counter.vhd
....................................................\........\.....................\...\tb.v
....................................................\........\.....................\...\top.v
....................................................\........\.....................\synth\isim.cmd
....................................................\........\.....................\.....\synth.xise
....................................................\........\.....................\.....\top.lso
....................................................\........\.....................\.....\top.ptwx
....................................................\........\.....................\.....\top.stx
....................................................\........\.....................\.....\top_map.mrp
....................................................\........\.8.verilog\rtl\verilog2001.v
....................................................\........\..........\synth\synth.xise
....................................................\........\..........\.....\verilog2001.lso
....................................................\........\..........\.....\verilog2001.stx
....................................................\........\..........\.....\verilog2001_map.mrp
....................................................\........\20.21.clocking\cores\.lso
....................................................\........\..............\.....\blk_mem.v
....................................................\........\..............\.....\blk_mem.xco
....................................................\........\..............\.....\clka_mmcm.v
....................................................\........\..............\.....\clka_mmcm.xco
....................................................\........\..

相关说明

  • 本站资源为会员上传分享交流与学习,如有侵犯您的权益,请联系我们删除.
  • 本站是交换下载平台,提供交流渠道,下载内容来自于网络,除下载问题外,其它问题请自行百度更多...
  • 请直接用浏览器下载本站内容,不要使用迅雷之类的下载软件,用WinRAR最新版进行解压.
  • 如果您发现内容无法下载,请稍后再次尝试;或者到消费记录里找到下载记录反馈给我们.
  • 下载后发现下载的内容跟说明不相乎,请到消费记录里找到下载记录反馈给我们,经确认后退回积分.
  • 如下载前有疑问,可以通过点击"提供者"的名字,查看对方的联系方式,联系对方咨询.

相关评论

暂无评论内容.

发表评论

*主  题:
*内  容:
*验 证 码:

源码中国 www.ymcn.org