文件名称:UART_16750_vhdl
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UART串口FPGA源文件，VHDL设计文件，兼容16750-UART FPGA VHDL 16750
(系统自动生成,下载前可以参看下载内容)
下载文件列表
vhdl\slib_clock_div.vhd
....\slib_counter.vhd
....\slib_edge_detect.vhd
....\slib_fifo.vhd
....\slib_fifo_cyclone2.vhd
....\slib_input_filter.vhd
....\slib_input_sync.vhd
....\slib_mv_filter.vhd
....\uart_16750.vhd
....\uart_baudgen.vhd
....\uart_interrupt.vhd
....\uart_receiver.vhd
....\uart_transmitter.vhd
vhdl