文件名称:20161203_hh
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MD5认证部分的第三轮中包含H函数的一次操作的FPGA实现源代码，采用Verilog，在Quartus II上综合-FPGA third round included H functions in one operation MD5 authentication component implementation source code, using Verilog, synthesis in Quartus II
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下载文件列表
20161203_hh\db\hh.cbx.xml
...........\..\hh.cmp.rdb
...........\..\hh.cmp_merge.kpt
...........\..\hh.db_info
...........\..\hh.eda.qmsg
...........\..\hh.hier_info
...........\..\hh.hif
...........\..\hh.lpc.html
...........\..\hh.lpc.rdb
...........\..\hh.lpc.txt
...........\..\hh.map.bpm
...........\..\hh.map.cdb
...........\..\hh.map.hdb
...........\..\hh.map.kpt
...........\..\hh.map.logdb
...........\..\hh.map.qmsg
...........\..\hh.map.rdb
...........\..\hh.map_bb.cdb
...........\..\hh.map_bb.hdb
...........\..\hh.map_bb.logdb
...........\..\hh.pre_map.cdb
...........\..\hh.pre_map.hdb
...........\..\hh.root_partition.map.reg_db.cdb
...........\..\hh.rtlv.hdb
...........\..\hh.rtlv_sg.cdb
...........\..\hh.rtlv_sg_swap.cdb
...........\..\hh.sgdiff.cdb
...........\..\hh.sgdiff.hdb
...........\..\hh.sld_design_entry.sci
...........\..\hh.sld_design_entry_dsc.sci
...........\..\hh.smart_action.txt
...........\..\hh.syn_hier_info
...........\..\hh.tis_db_list.ddb
...........\..\hh.tmw_info
...........\..\logic_util_heursitic.dat
...........\..\prev_cmp_hh.qmsg
...........\hh.done
...........\hh.eda.rpt
...........\hh.flow.rpt
...........\hh.map.rpt
...........\hh.map.summary
...........\hh.qpf
...........\hh.qsf
...........\hh.qws
...........\hh.v
...........\hh.v.bak
...........\hh_nativelink_simulation.rpt
...........\incremental_db\compiled_partitions\hh.db_info
...........\..............\...................\hh.root_partition.map.cdb
...........\..............\...................\hh.root_partition.map.dpi
...........\..............\...................\hh.root_partition.map.hbdb.cdb
...........\..............\...................\hh.root_partition.map.hbdb.hb_info
...........\..............\...................\hh.root_partition.map.hbdb.hdb
...........\..............\...................\hh.root_partition.map.hbdb.sig
...........\..............\...................\hh.root_partition.map.hdb
...........\..............\...................\hh.root_partition.map.kpt
...........\..............\README
...........\simulation\modelsim\hh.vt
...........\..........\........\hh.vt.bak
...........\..........\........\hh_run_msim_rtl_verilog.do
...........\..........\........\hh_run_msim_rtl_verilog.do.bak
...........\..........\........\hh_run_msim_rtl_verilog.do.bak1
...........\..........\........\hh_run_msim_rtl_verilog.do.bak2
...........\..........\........\modelsim.ini
...........\..........\........\msim_transcript
...........\..........\........\rtl_work\hh\verilog.prw
...........\..........\........\........\..\verilog.psm
...........\..........\........\........\..\_primary.dat
...........\..........\........\........\..\_primary.dbs
...........\..........\........\........\..\_primary.vhd
...........\..........\........\........\.._vlg_tst\verilog.prw
...........\..........\........\........\..........\verilog.psm
...........\..........\........\........\..........\_primary.dat
...........\..........\........\........\..........\_primary.dbs
...........\..........\........\........\..........\_primary.vhd
...........\..........\........\........\_info
...........\..........\........\........\_vmake
...........\..........\........\vsim.wlf
...........\..........\........\rtl_work\hh
...........\..........\........\........\hh_vlg_tst
...........\..........\........\........\_temp
...........\..........\........\rtl_work
...........\incremental_db\compiled_partitions
...........\simulation\modelsim
...........\db
...........\incremental_db
...........\simulation
20161203_hh