文件名称:20161122_gg
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MD5认证部分的第二轮中包含G函数的一次操作的FPGA实现源代码，采用Verilog，在Quartus II上综合-FPGA contains one operation in the second round of the G function MD5 authentication component implementation source code, using Verilog, synthesis in Quartus II
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下载文件列表
20161122_gg\db\gg.cbx.xml
...........\..\gg.cmp.rdb
...........\..\gg.cmp_merge.kpt
...........\..\gg.db_info
...........\..\gg.eda.qmsg
...........\..\gg.hier_info
...........\..\gg.hif
...........\..\gg.lpc.html
...........\..\gg.lpc.rdb
...........\..\gg.lpc.txt
...........\..\gg.map.bpm
...........\..\gg.map.cdb
...........\..\gg.map.hdb
...........\..\gg.map.kpt
...........\..\gg.map.logdb
...........\..\gg.map.qmsg
...........\..\gg.map.rdb
...........\..\gg.map_bb.cdb
...........\..\gg.map_bb.hdb
...........\..\gg.map_bb.logdb
...........\..\gg.pre_map.cdb
...........\..\gg.pre_map.hdb
...........\..\gg.root_partition.map.reg_db.cdb
...........\..\gg.rtlv.hdb
...........\..\gg.rtlv_sg.cdb
...........\..\gg.rtlv_sg_swap.cdb
...........\..\gg.sgdiff.cdb
...........\..\gg.sgdiff.hdb
...........\..\gg.sld_design_entry.sci
...........\..\gg.sld_design_entry_dsc.sci
...........\..\gg.smart_action.txt
...........\..\gg.syn_hier_info
...........\..\gg.tis_db_list.ddb
...........\..\gg.tmw_info
...........\..\logic_util_heursitic.dat
...........\..\prev_cmp_gg.qmsg
...........\gg.done
...........\gg.eda.rpt
...........\gg.flow.rpt
...........\gg.map.rpt
...........\gg.map.summary
...........\gg.qpf
...........\gg.qsf
...........\gg.qws
...........\gg.v
...........\gg.v.bak
...........\gg_nativelink_simulation.rpt
...........\incremental_db\compiled_partitions\gg.db_info
...........\..............\...................\gg.root_partition.map.cdb
...........\..............\...................\gg.root_partition.map.dpi
...........\..............\...................\gg.root_partition.map.hbdb.cdb
...........\..............\...................\gg.root_partition.map.hbdb.hb_info
...........\..............\...................\gg.root_partition.map.hbdb.hdb
...........\..............\...................\gg.root_partition.map.hbdb.sig
...........\..............\...................\gg.root_partition.map.hdb
...........\..............\...................\gg.root_partition.map.kpt
...........\..............\README
...........\simulation\modelsim\gg.vt
...........\..........\........\gg.vt.bak
...........\..........\........\gg_run_msim_rtl_verilog.do
...........\..........\........\gg_run_msim_rtl_verilog.do.bak
...........\..........\........\modelsim.ini
...........\..........\........\msim_transcript
...........\..........\........\rtl_work\gg\verilog.prw
...........\..........\........\........\..\verilog.psm
...........\..........\........\........\..\_primary.dat
...........\..........\........\........\..\_primary.dbs
...........\..........\........\........\..\_primary.vhd
...........\..........\........\........\.._vlg_tst\verilog.prw
...........\..........\........\........\..........\verilog.psm
...........\..........\........\........\..........\_primary.dat
...........\..........\........\........\..........\_primary.dbs
...........\..........\........\........\..........\_primary.vhd
...........\..........\........\........\_info
...........\..........\........\........\_vmake
...........\..........\........\vsim.wlf
...........\..........\........\rtl_work\gg
...........\..........\........\........\gg_vlg_tst
...........\..........\........\........\_temp
...........\..........\........\rtl_work
...........\incremental_db\compiled_partitions
...........\simulation\modelsim
...........\db
...........\incremental_db
...........\simulation
20161122_gg