文件名称:VERILOG-Simulation
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This VERILOG simulation example shows a 16 bit group ripple adder circuit for FPGA. The netlabel is used to split 16 bit bus to four 4 bit bus and connect them to four 4 bit adder. The result is joined to a 16 bit bus using netlabel. The Simulation can be done in the built-in Aldec OEM simulator in Altium Designer.
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下载文件列表
VERILOG Simulation
..................\16Bit Group Ripple Adder
..................\........................\16Bit Group Ripple Adder.PrjFpg
..................\........................\16Bit Group Ripple Adder.PrjFpgStructure
..................\........................\16Bit Group Ripple Adder.SchDoc
..................\........................\TestBench.v
..................\BCD Counter
..................\...........\BCD.v
..................\...........\BCD8.PrjFpg
..................\...........\BCD8.PrjFpgStructure
..................\...........\BCD8.schdoc
..................\...........\parity.v
..................\...........\TestBench.v
..................\Error Correcting For 7bit Hamming Code
..................\......................................\decoder.v
..................\......................................\Error Correcting For 7bit Hamming Code.PrjFpg
..................\......................................\Error Correcting For 7bit Hamming Code.PrjFpgStructure
..................\......................................\Error Correcting For 7bit Hamming Code.SchDoc
..................\......................................\parity.v
..................\......................................\TestBench.v
..................\Frequency Meter
..................\...............\Control.SchDoc
..................\...............\Four Bit Decimal Counter ConfigCnt.SchDoc
..................\...............\Four Bit Decimal Counter.SchDoc
..................\...............\Four Decade BCD Counter.SchDoc
..................\...............\Frequency Meter.PrjFpg
..................\...............\Frequency Meter.PrjFpgStructure
..................\...............\Frequency Meter.SchDoc
..................\...............\hex7segment.v
..................\...............\TestBench.v
..................\KeyBoard Reader
..................\...............\KeyBrdReader.PrjFpg
..................\...............\KeyBrdReader.PrjFpgStructure
..................\...............\KeyBrdReader.SchDoc
..................\...............\TestBench.v
..................\Parallel To Serial Converter
..................\............................\Parallel To Serial Converter Bus.SchDoc
..................\............................\Parallel To Serial Converter.PrjFpg
..................\............................\Parallel To Serial Converter.PrjFpgStructure
..................\............................\Parallel To Serial Converter.SchDoc
..................\............................\shift_reg_bitblasted.v
..................\............................\TestBench.v
..................\Pulse Width Modulation
..................\......................\pwm.PrjFpg
..................\......................\pwm.PrjFpgStructure
..................\......................\pwm.schdoc
..................\......................\sch_pwm.schdoc
..................\......................\TestBench.v
..................\Serial To Parallel Converter
..................\............................\Serial To Parallel Converter.PrjFpg
..................\............................\Serial To Parallel Converter.PrjFpgStructure
..................\............................\Serial To Parallel Converter.SchDoc
..................\............................\SR8CES.v
..................\............................\TestBench.v
..................\Test BarLed Window
..................\..................\mux16.v
..................\..................\TBarLedWindow.PRJFPG
..................\..................\TBarLedWindow.PRJFPGStructure
..................\..................\TBarLedWindow.schDOC
..................\..................\TestBench.v
..................\..................\TMouseEvent.schDoc
..................\..................\TRange.v
..................\..................\TWindow.schDoc
..................\Test Control Window
..................\...................\JK_FF.v
..................\...................\TControl.schDOC
..................\...................\TControlWindow.PrjFpg
..................\...................\TControlWindow.PrjFpgStructure
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