文件名称:20_lcd
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FPGA实现LCD显示，verilog编程控制-FPGA achieve LCD display, Verilog programming control
(系统自动生成,下载前可以参看下载内容)
下载文件列表
20_lcd
......\20_lcd.asm.rpt
......\20_lcd.cdf
......\20_lcd.done
......\20_lcd.fit.rpt
......\20_lcd.fit.smsg
......\20_lcd.fit.summary
......\20_lcd.flow.rpt
......\20_lcd.jdi
......\20_lcd.map.rpt
......\20_lcd.map.smsg
......\20_lcd.map.summary
......\20_lcd.pin
......\20_lcd.pof
......\20_lcd.qpf
......\20_lcd.qsf
......\20_lcd.qws
......\20_lcd.sof
......\20_lcd.sta.rpt
......\20_lcd.sta.summary
......\20_lcd_assignment_defaults.qdf
......\db
......\..\.cmp.kpt
......\..\20_lcd.asm.qmsg
......\..\20_lcd.asm.rdb
......\..\20_lcd.asm_labs.ddb
......\..\20_lcd.cbx.xml
......\..\20_lcd.cmp.bpm
......\..\20_lcd.cmp.cdb
......\..\20_lcd.cmp.hdb
......\..\20_lcd.cmp.idb
......\..\20_lcd.cmp.logdb
......\..\20_lcd.cmp.rdb
......\..\20_lcd.cmp_merge.kpt
......\..\20_lcd.cycloneive_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
......\..\20_lcd.cycloneive_io_sim_cache.31um_ss_1200mv_0c_slow.hsd
......\..\20_lcd.cycloneive_io_sim_cache.31um_ss_1200mv_85c_slow.hsd
......\..\20_lcd.db_info
......\..\20_lcd.fit.qmsg
......\..\20_lcd.hier_info
......\..\20_lcd.hif
......\..\20_lcd.ipinfo
......\..\20_lcd.lpc.html
......\..\20_lcd.lpc.rdb
......\..\20_lcd.lpc.txt
......\..\20_lcd.map.ammdb
......\..\20_lcd.map.bpm
......\..\20_lcd.map.cdb
......\..\20_lcd.map.hdb
......\..\20_lcd.map.kpt
......\..\20_lcd.map.logdb
......\..\20_lcd.map.qmsg
......\..\20_lcd.map.rdb
......\..\20_lcd.map_bb.cdb
......\..\20_lcd.map_bb.hdb
......\..\20_lcd.map_bb.logdb
......\..\20_lcd.npp.qmsg
......\..\20_lcd.pre_map.hdb
......\..\20_lcd.pti_db_list.ddb
......\..\20_lcd.root_partition.map.reg_db.cdb
......\..\20_lcd.routing.rdb
......\..\20_lcd.rtlv.hdb
......\..\20_lcd.rtlv_sg.cdb
......\..\20_lcd.rtlv_sg_swap.cdb
......\..\20_lcd.sgate.nvd
......\..\20_lcd.sgate_sm.nvd
......\..\20_lcd.sgdiff.cdb
......\..\20_lcd.sgdiff.hdb
......\..\20_lcd.sld_design_entry.sci
......\..\20_lcd.sld_design_entry_dsc.sci
......\..\20_lcd.smart_action.txt
......\..\20_lcd.sta.qmsg
......\..\20_lcd.sta.rdb
......\..\20_lcd.sta_cmp.8_slow_1200mv_85c.tdb
......\..\20_lcd.tis_db_list.ddb
......\..\20_lcd.tiscmp.fast_1200mv_0c.ddb
......\..\20_lcd.tiscmp.fastest_slow_1200mv_0c.ddb
......\..\20_lcd.tiscmp.fastest_slow_1200mv_85c.ddb
......\..\20_lcd.tiscmp.slow_1200mv_0c.ddb
......\..\20_lcd.tiscmp.slow_1200mv_85c.ddb
......\..\20_lcd.tmw_info
......\..\20_lcd.vpr.ammdb
......\..\altsyncram_10i1.tdf
......\..\altsyncram_60i1.tdf
......\..\altsyncram_h5c1.tdf
......\..\logic_util_heursitic.dat
......\..\prev_cmp_20_lcd.qmsg
......\greybox_tmp
......\...........\cbx_args.txt
......\incremental_db
......\..............\README
......\..............\compiled_partitions
......\..............\...................\20_lcd.db_info
......\..............\...................\20_lcd.root_partition.cmp.ammdb
......\..............\...................\20_lcd.root_partition.cmp.cdb
......\..............\...................\20_lcd.root_partition.cmp.dfp
......\..............\...................\20_lcd.root_partition.cmp.hdb
......\..............\...................\20_lcd.root_partition.cmp.kpt
......\..............\...................\20_lcd.root_partition.cmp.logdb
......\..............\...................\20_lcd.root_partition.cmp.rcfdb