文件名称:Fibonacci
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（1） clkdiv 模块：对50MHz 系统时钟 进行分频，分别得到190Hz，3Hz
信号。190Hz 信号用于动态扫描模块位选信号，3Hz 信号用于fib 模块。
（2） fib 模块：依据实验原理所述Fibonacci 数列原理，用VHDL 语言实现数列
（3） binbcd14：实现二进制码到BCD 码的转换，用于数码管显示。
（4） x7segbc：采用动态扫描，使用4 位数码管依次显示Fibonacci 数列数据。
实验采用3Hz 频率来产生Fibonacci 数列，因而显示频率较快，设计者可根据需要修改
程序，使得数列产生速度减慢，如可使用1Hz，或者更慢的速度，以便能在数码管上清晰的观察到Fibonacci 数列的变换过程。，-(1) clkdiv module: the 50MHz system clock system clock frequency, were 190Hz, 3Hz
signal. The 190 Hz signal is used to dynamically scan the module bit signal and the 3 Hz signal is used for the fib module.
(2) fib module: According to the experimental principle described in the principle of Fibonacci series, with VHDL language series
(3) binbcd14: Binary code to achieve the BCD code conversion, for digital display.
(4) x7segbc: the use of dynamic scanning, the use of four digital display Fibonacci sequence data in turn.
Experiments using 3Hz frequency to generate Fibonacci sequence, which shows a faster frequency, the designer may need to modify
Program, making the series produced slower, such as can be used 1Hz, or slower speed, so that the digital tube can be clear
The transformation process of the Fibonacci sequence is observed. , & Lt
信号。190Hz 信号用于动态扫描模块位选信号，3Hz 信号用于fib 模块。
（2） fib 模块：依据实验原理所述Fibonacci 数列原理，用VHDL 语言实现数列
（3） binbcd14：实现二进制码到BCD 码的转换，用于数码管显示。
（4） x7segbc：采用动态扫描，使用4 位数码管依次显示Fibonacci 数列数据。
实验采用3Hz 频率来产生Fibonacci 数列，因而显示频率较快，设计者可根据需要修改
程序，使得数列产生速度减慢，如可使用1Hz，或者更慢的速度，以便能在数码管上清晰的观察到Fibonacci 数列的变换过程。，-(1) clkdiv module: the 50MHz system clock system clock frequency, were 190Hz, 3Hz
signal. The 190 Hz signal is used to dynamically scan the module bit signal and the 3 Hz signal is used for the fib module.
(2) fib module: According to the experimental principle described in the principle of Fibonacci series, with VHDL language series
(3) binbcd14: Binary code to achieve the BCD code conversion, for digital display.
(4) x7segbc: the use of dynamic scanning, the use of four digital display Fibonacci sequence data in turn.
Experiments using 3Hz frequency to generate Fibonacci sequence, which shows a faster frequency, the designer may need to modify
Program, making the series produced slower, such as can be used 1Hz, or slower speed, so that the digital tube can be clear
The transformation process of the Fibonacci sequence is observed. , & Lt
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下载文件列表
Fibonacci\.lso
.........\binbcd14.vhd
.........\clkdiv.vhd
.........\device_usage_statistics.html
.........\fib.ise
.........\fib.ntrc_log
.........\fib.restore
.........\fib.vhd
.........\fib_isim_beh.wfs
.........\fib_top.bgn
.........\fib_top.bit
.........\fib_top.bld
.........\fib_top.cmd_log
.........\fib_top.drc
.........\fib_top.lfp
.........\fib_top.lso
.........\fib_top.ncd
.........\fib_top.ngc
.........\fib_top.ngd
.........\fib_top.ngr
.........\fib_top.pad
.........\fib_top.par
.........\fib_top.pcf
.........\fib_top.prj
.........\fib_top.ptwx
.........\fib_top.stx
.........\fib_top.syr
.........\fib_top.twr
.........\fib_top.twx
.........\fib_top.ucf
.........\fib_top.unroutes
.........\fib_top.ut
.........\fib_top.vhd
.........\fib_top.xpi
.........\fib_top.xst
.........\fib_top_guide.ncd
.........\fib_top_map.map
.........\fib_top_map.mrp
.........\fib_top_map.ncd
.........\fib_top_map.ngm
.........\fib_top_map.xrpt
.........\fib_top_ngdbuild.xrpt
.........\fib_top_pad.csv
.........\fib_top_pad.txt
.........\fib_top_par.xrpt
.........\fib_top_prev_built.ngd
.........\fib_top_summary.html
.........\fib_top_summary.xml
.........\fib_top_usage.xml
.........\fib_top_vhdl.prj
.........\fib_top_xst.xrpt
.........\fib_vhdl.prj
.........\....xdb\cst.xbcd
.........\.......\tmp\ise\version
.........\.......\...\...\__OBJSTORE__\HierarchicalDesign\HDProject\HDProject
.........\.......\...\...\............\..................\.........\HDProject_StrTbl
.........\.......\...\...\............\..................\__stored_object_table__
.........\.......\...\...\............\ISimPlugin\SignalOrdering1\testtop_isim_beh.exe
.........\.......\...\...\............\..........\...............\testtop_isim_beh.exe_StrTbl
.........\.......\...\...\............\..........\...............\test_isim_beh.exe
.........\.......\...\...\............\..........\...............\test_isim_beh.exe_StrTbl
.........\.......\...\...\............\PnAutoRun\Scripts\RunOnce_tcl
.........\.......\...\...\............\.........\.......\RunOnce_tcl_StrTbl
.........\.......\...\...\............\.rojectNavigator\dpm_project_main\dpm_project_main
.........\.......\...\...\............\................\................\dpm_project_main_StrTbl
.........\.......\...\...\............\................\................\NameMap
.........\.......\...\...\............\................\................\NameMap_StrTbl
.........\.......\...\...\............\................\__stored_objects__
.........\.......\...\...\............\................\__stored_objects___StrTbl
.........\.......\...\...\............\................\__stored_object_table__
.........\.......\...\...\............\................Gui\GuiProjectData
.........\.......\...\...\............\...................\GuiProjectData_StrTbl
.........\.......\...\...\............\xreport\Gc_RvReportViewer-Current-Module
.........\.......\...\...\............\.......\Gc_RvReportViewer-Current-Module_StrTbl
.........\.......\...\...\............\.......\Gc_RvReportViewer-Module-Data-fib_top
.........\.......\...\...\............\.......\Gc_RvReportViewer-Module-Data-fib_top_StrTbl
.........\.......\...\...\............\.......\Gc_RvReportViewer-Module-DataFactory-Default
.........\.......\...\...\............\.......\Gc_RvReportViewer-Module-DataFactory-Default_StrTbl
.........\.......\...\...\..REGISTRY__\Autonym\regkeys
.........\.......\...\...\............\bitgen\regkeys
.........\.......\...\...\............\common\regkeys
.........\.......\...\...\............\.pldfit\regkeys
.........\.......\...\...\............\Cs\regkeys
.........\.......\...\...\............\dumpngdio\regkeys
.........\.......\...\...\............\ExpandedNetlistEngine\regkeys
.........\.......\...\...\............\fuse\regkeys
.........\.......\...\...\............\HierarchicalDesign\HDProject\regkeys
.........\.......\...\...\............\..................\regkeys
.........\.......\...\...\............\hprep6\regkeys
.........\.......\...\...\............\idem\regkeys
.........\.......\...\...\............\ISimPlugin\re