文件名称:fp_adder_subtractor
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本文介绍用于计算IEEE 754标准的双精度64位浮点二进制数加/减法硬件架构。-In this article, an optimized pipeline
hardware architecture for computing IEEE 754 standard
double precision 64-bit floating point binary number
addition/subtraction was proposed.
hardware architecture for computing IEEE 754 standard
double precision 64-bit floating point binary number
addition/subtraction was proposed.
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fp_adder_subtractor.pdf