文件名称:AMBA
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AMBA总线的Verilog语言模型，主要包括5个部分：AHB总线仲裁器，AHB-APB总线桥接器，AHB总线上从设备ROM模型-AMBA bus of ARM company, It mainly includes the following five parts: the AHB arbiter,AHB-APB bridge, AHB_Rom_Slave, AHB_Ram_Slave
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下载文件列表
ahb_apb_bridge\rtl\ahb_apb_bridge.v
.....rbiter\rtl\ahb_arbiter.v
...........\...\ahb_decoder.v
...........\...\ahb_default_master.v
...........\...\ahb_default_slave.v
...........\...\ahb_mast_mux.v
...........\...\ahb_slave_mux.v
....rom_slave\rtl\ahb_rom_slave.v
....sram_slave\rtl\ahb_sram_slave.v
defines\ahb_defines.v
.......\apb_defines.v
ahb_apb_bridge\rtl
.....rbiter\rtl
....rom_slave\rtl
....sram_slave\rtl
ahb_apb_bridge
ahb_arbiter
ahb_rom_slave
ahb_sram_slave
defines