文件名称:MEM
介绍说明－－下载内容均来自于网络，请自行研究使用
hereby i have attached memory controller vip by using system verilog hope this will be helpfule for u
(系统自动生成,下载前可以参看下载内容)
下载文件列表
MEM\design\rtl\CVS\Entries
...\......\...\...\Repository
...\......\...\...\Root
...\......\...\verilog\.mc_adr_sel.v.swo
...\......\...\.......\.mc_top.v.swn
...\......\...\.......\CVS\Entries
...\......\...\.......\...\Repository
...\......\...\.......\...\Root
...\......\...\.......\mc_adr_sel.v
...\......\...\.......\mc_cs_rf.v
...\......\...\.......\mc_defines.v
...\......\...\.......\mc_dp.v
...\......\...\.......\mc_incn_r.v
...\......\...\.......\mc_mem_if.v
...\......\...\.......\mc_obct.v
...\......\...\.......\mc_obct_top.v
...\......\...\.......\mc_rd_fifo.v
...\......\...\.......\mc_refresh.v
...\......\...\.......\mc_rf.v
...\......\...\.......\mc_timing.v
...\......\...\.......\mc_top.v
...\......\...\.......\mc_wb_if.v
...\......\...\.......\timescale.v
...\mc\mem_intf.sv
...\..\mem_intf.sv~
...\..\readme.txt
...\MemoryModels\160b3ver\adv_bb.v
...\............\........\dp160b3b.v
...\............\........\DP160B3B_RU.V
...\............\........\dp160b3t.v
...\............\........\f160b3b.bkb
...\............\........\f160b3b.bke
...\............\........\f160b3b.bkt
...\............\........\f160b3t.bkb
...\............\........\f160b3t.bke
...\............\........\f160b3t.bkt
...\............\........\read.me
...\............\........\t160b3b.v
...\............\........\t160b3t.v
...\............\sdram_models\16Mx16\mt48lc16m16a2.v
...\............\............\....8\mt48lc16m8a2.v
...\............\............\2Mx32\bank0.txt
...\............\............\.....\bank1.txt
...\............\............\.....\bank2.txt
...\............\............\.....\bank3.txt
...\............\............\.....\mt48lc2m32b2.v
...\............\............\32Mx8\mt48lc32m8a2.v
...\............\............\4Mx16\bank0.txt
...\............\............\.....\bank1.txt
...\............\............\.....\bank2.txt
...\............\............\.....\bank3.txt
...\............\............\.....\mt48lc4m16a2.v
...\............\............\...32\mt48lc4m32b2.v
...\............\............\8Mx16\mt48lc8m16a2.v
...\............\............\...8\bank0.txt
...\............\............\....\bank1.txt
...\............\............\....\bank2.txt
...\............\............\....\bank3.txt
...\............\............\....\mt48lc8m8a2.v
...\............\.ram_models\IDT71T67802\idt71t67802s133.v
...\............\...........\...........\idt71t67802s150.v
...\............\...........\...........\idt71t67802s166.v
...\............\...........\...........\idt_512Kx18_PBSRAM_test.v
...\............\...........\...........\readme_71T67802
...\............\...........\MicronSRAM\mt58l1my18d.v
...\............\SyncCS\.sync_cs_dev.v.swo
...\............\......\sync_cs_dev.v
...\top\modelsim.ini
...\...\run.do
...\...\run2.do
...\...\run2.do~
...\...\topsvh.svh
...\...\topsvh.svh~
...\...\vsim.wlf
...\...\wb_top.sv
...\...\wb_top.sv~
...\...\.ork\@intel@adv@boot\_primary.dat
...\...\....\...............\_primary.dbs
...\...\....\...............\_primary.vhd
...\...\....\mc_adr_sel\verilog.asm
...\...\....\..........\verilog.rw
...\...\....\..........\_primary.dat
...\...\....\..........\_primary.dbs
...\...\....\..........\_primary.vhd
...\...\....\...cs_rf\verilog.asm
...\...\....\........\verilog.rw
...\...\....\........\_primary.dat
...\...\....\........\_primary.dbs
...\...\....\........\_primary.vhd
...\...\....\........_dummy\_primary.dat
...\...\....\..............\_primary.dbs
...\...\....\..............\_primary.vhd
...\...\....\...dp\verilog.asm
...\...\....\.....\verilog.rw
...\...\....\.....\_primary.dat
...\...\....\.....\_primary.dbs
...\...\....\.....\_primary.vhd
...\...\....\...incn_r\verilog.asm
...\...\....\.........\verilog.rw
...\...\....\.........\_primary.dat