文件名称:My-And
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And port made with nand gates in Verilog
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下载文件列表
My And
......\db
......\..\logic_util_heursitic.dat
......\..\my_and.cbx.xml
......\..\my_and.cmp.rdb
......\..\my_and.cmp_merge.kpt
......\..\my_and.db_info
......\..\my_and.hier_info
......\..\my_and.hif
......\..\my_and.ipinfo
......\..\my_and.lpc.html
......\..\my_and.lpc.rdb
......\..\my_and.lpc.txt
......\..\my_and.map.ammdb
......\..\my_and.map.bpm
......\..\my_and.map.cdb
......\..\my_and.map.hdb
......\..\my_and.map.kpt
......\..\my_and.map.logdb
......\..\my_and.map.qmsg
......\..\my_and.map.rdb
......\..\my_and.map_bb.cdb
......\..\my_and.map_bb.hdb
......\..\my_and.map_bb.logdb
......\..\my_and.pre_map.hdb
......\..\my_and.pti_db_list.ddb
......\..\my_and.root_partition.map.reg_db.cdb
......\..\my_and.rtlv.hdb
......\..\my_and.rtlv_sg.cdb
......\..\my_and.rtlv_sg_swap.cdb
......\..\my_and.sgdiff.cdb
......\..\my_and.sgdiff.hdb
......\..\my_and.sld_design_entry.sci
......\..\my_and.sld_design_entry_dsc.sci
......\..\my_and.smart_action.txt
......\..\my_and.syn_hier_info
......\..\my_and.tis_db_list.ddb
......\..\my_and.tmw_info
......\..\prev_cmp_my_and.qmsg
......\incremental_db
......\..............\compiled_partitions
......\..............\...................\my_and.db_info
......\..............\...................\my_and.root_partition.map.cdb
......\..............\...................\my_and.root_partition.map.dpi
......\..............\...................\my_and.root_partition.map.hbdb.cdb
......\..............\...................\my_and.root_partition.map.hbdb.hb_info
......\..............\...................\my_and.root_partition.map.hbdb.hdb
......\..............\...................\my_and.root_partition.map.hbdb.sig
......\..............\...................\my_and.root_partition.map.hdb
......\..............\...................\my_and.root_partition.map.kpt
......\..............\README
......\my_and.qpf
......\my_and.qsf
......\my_and.qws
......\my_and.v
......\my_and_model.do
......\my_and_nativelink_simulation.rpt
......\output_files
......\............\my_and.done
......\............\my_and.flow.rpt
......\............\my_and.map.rpt
......\............\my_and.map.summary
......\simulation
......\..........\modelsim
......\..........\........\modelsim.ini
......\..........\........\msim_transcript
......\..........\........\My And.cr.mti
......\..........\........\My And.mpf
......\..........\........\my_and_run_msim_rtl_verilog.do
......\..........\........\rtl_work
......\..........\........\........\my_and
......\..........\........\........\......\verilog.prw
......\..........\........\........\......\verilog.psm
......\..........\........\........\......\_primary.dat
......\..........\........\........\......\_primary.dbs
......\..........\........\........\......\_primary.vhd
......\..........\........\........\_info
......\..........\........\........\_temp
......\..........\........\........\_vmake
......\..........\........\transcript
......\..........\........\work
......\..........\........\....\my_and
......\..........\........\....\......\verilog.prw
......\..........\........\....\......\verilog.psm
......\..........\........\....\......\_primary.dat
......\..........\........\....\......\_primary.dbs
......\..........\........\....\......\_primary.vhd
......\..........\........\....\stimulus
......\..........\........\....\........\verilog.prw
......\..........\........\....\........\verilog.psm
......\..........\........\....\........\_primary.dat
......\..........\........\....\........\_primary.dbs
......\..........\........\....\........\_primary.vhd
......\..........\........\....\_info
......\..........\........\....\_temp
......\..........\........\....\_vmake
......\stimulus.v
......\stimulus.v.bak
......\work
......\....\my_and