文件名称:practica1
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tester.vhd
library IEEE
use IEEE.STD_LOGIC_1164.all
use IEEE.STD_LOGIC_ARITH.all
use IEEE.STD_LOGIC_UNSIGNED.all
LIBRARY lpm
USE lpm.lpm_components.ALL
entity practica1 is
port (
RESET : in std_logic
clk : in std_logic
ena_mem : in std_logic
sel_m : in std_logic
q : out std_logic_vector (5 downto 0))
end practica1
architecture operation of practica1 is
signal address_2 : std_logic_vector(5 downto 0)
begin
process(clk, ena_mem, RESET, sel_m)
begin
if (RESET = 0 ) then
address_2 <= (others => 0 )
elsif rising_edge(clk) then
if ena_mem = 1 and sel_m = 1 then
address_2 <= address_2 + 1
q <= address_2
end if
end if
end process
end operation
- tester.vhd
library IEEE
use IEEE.STD_LOGIC_1164.all
use IEEE.STD_LOGIC_ARITH.all
use IEEE.STD_LOGIC_UNSIGNED.all
LIBRARY lpm
USE lpm.lpm_components.ALL
entity practica1 is
port (
RESET : in std_logic
clk : in std_logic
ena_mem : in std_logic
sel_m : in std_logic
q : out std_logic_vector (5 downto 0))
end practica1
architecture operation of practica1 is
signal address_2 : std_logic_vector(5 downto 0)
begin
process(clk, ena_mem, RESET, sel_m)
begin
if (RESET = 0 ) then
address_2 <= (others => 0 )
elsif rising_edge(clk) then
if ena_mem = 1 and sel_m = 1 then
address_2 <= address_2 + 1
q <= address_2
end if
end if
end process
end operation
library IEEE
use IEEE.STD_LOGIC_1164.all
use IEEE.STD_LOGIC_ARITH.all
use IEEE.STD_LOGIC_UNSIGNED.all
LIBRARY lpm
USE lpm.lpm_components.ALL
entity practica1 is
port (
RESET : in std_logic
clk : in std_logic
ena_mem : in std_logic
sel_m : in std_logic
q : out std_logic_vector (5 downto 0))
end practica1
architecture operation of practica1 is
signal address_2 : std_logic_vector(5 downto 0)
begin
process(clk, ena_mem, RESET, sel_m)
begin
if (RESET = 0 ) then
address_2 <= (others => 0 )
elsif rising_edge(clk) then
if ena_mem = 1 and sel_m = 1 then
address_2 <= address_2 + 1
q <= address_2
end if
end if
end process
end operation
- tester.vhd
library IEEE
use IEEE.STD_LOGIC_1164.all
use IEEE.STD_LOGIC_ARITH.all
use IEEE.STD_LOGIC_UNSIGNED.all
LIBRARY lpm
USE lpm.lpm_components.ALL
entity practica1 is
port (
RESET : in std_logic
clk : in std_logic
ena_mem : in std_logic
sel_m : in std_logic
q : out std_logic_vector (5 downto 0))
end practica1
architecture operation of practica1 is
signal address_2 : std_logic_vector(5 downto 0)
begin
process(clk, ena_mem, RESET, sel_m)
begin
if (RESET = 0 ) then
address_2 <= (others => 0 )
elsif rising_edge(clk) then
if ena_mem = 1 and sel_m = 1 then
address_2 <= address_2 + 1
q <= address_2
end if
end if
end process
end operation
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practica1