文件名称:mig_7series_v1_9
介绍说明－－下载内容均来自于网络，请自行研究使用
DDR3控制器源码，针对XilinxFPGA的DDR3控制器的源码，已经验证通过。-DDR3 Controller，complete DDR3 controll，have pass verificaion.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
mig_7series_v1_9
................\datasheet.txt
................\docs
................\....\phy_only_support_readme.txt
................\....\ug586_7Series_MIS.pdf
................\example_design
................\..............\log.txt
................\..............\par
................\..............\...\create_ise.bat
................\..............\...\ddr_icon_cg.xco
................\..............\...\ddr_ila_basic_cg.xco
................\..............\...\ddr_ila_rdpath_cg.xco
................\..............\...\ddr_ila_wrpath_cg.xco
................\..............\...\ddr_vio_async_in_sync_out_cg.xco
................\..............\...\ddr_vio_sync_async_out72_cg.xco
................\..............\...\example_top.cpj
................\..............\...\example_top.ucf
................\..............\...\example_top.xdc
................\..............\...\ise_flow.bat
................\..............\...\makeproj.bat
................\..............\...\readme.txt
................\..............\...\rem_files.bat
................\..............\...\rem_files.tcl
................\..............\...\set_ise_prop.tcl
................\..............\...\xst_options.txt
................\..............\rtl
................\..............\...\example_top.v
................\..............\...\traffic_gen
................\..............\...\...........\mig_7series_v1_9_axi4_tg.v
................\..............\...\...........\mig_7series_v1_9_axi4_wrapper.v
................\..............\...\...........\mig_7series_v1_9_cmd_prbs_gen_axi.v
................\..............\...\...........\mig_7series_v1_9_data_gen_chk.v
................\..............\...\...........\mig_7series_v1_9_tg.v
................\..............\sim
................\..............\...\ddr3_model.v
................\..............\...\ddr3_model_parameters.vh
................\..............\...\isim_files.prj
................\..............\...\isim_options.tcl
................\..............\...\isim_run.bat
................\..............\...\readme.txt
................\..............\...\sim.do
................\..............\...\sim.do.bak
................\..............\...\sim_tb_top.v
................\..............\...\sim_tb_top.v.bak
................\..............\...\vsim.wlf
................\..............\...\wave.do
................\..............\...\wiredly.v
................\user_design\rtl\ui\mig_7series_v1_9_ui_top.v
................\...........\...\..\mig_7series_v1_9_ui_rd_data.v
................\...........\...\..\mig_7series_v1_9_ui_cmd.v
................\example_design\sim\work
................\..............\...\....\_info
................\..............\...\....\_lib.qdb
................\..............\...\....\_lib1_2.qdb
................\..............\...\....\_lib1_2.qpg
................\..............\...\....\_lib1_2.qtl
................\..............\...\....\_vmake
................\..............\...\xsim_files.prj
................\..............\...\xsim_options.tcl
................\..............\...\xsim_run.bat
................\..............\synth
................\..............\.....\example_top.lso
................\..............\.....\example_top.prj
................\..............\.....\synplify_pro.tcl
................\mig.prj
................\mig_7series_v1_9.csv
................\user_design
................\...........\constraints
................\...........\...........\mig_7series_v1_9.ucf
................\...........\...........\mig_7series_v1_9.xdc
................\...........\log.txt
................\...........\rtl
................\...........\...\axi
................\...........\...\...\mig_7series_v1_9_axi_ctrl_addr_decode.v
................\...........\...\...\mig_7series_v1_9_axi_ctrl_read.v
................\...........\...\...\mig_7series_v1_9_axi_ctrl_reg.v
................\...........\...\...\mig_7series_v1_9_axi_ctrl_reg_bank.v
................\...........\...\...\mig_7series_v1_9_axi_ctrl_top.v
................\...........\...\...\mig_7series_v1_9_axi_ctrl_write.v
................\.....