文件名称:Lab01
介绍说明－－下载内容均来自于网络，请自行研究使用
verilog 入门练习，包括完整的Verilog实例，包括仿真的所有文件，主要是关于寄存器定义、名称映射、RS触发器定义等内容-verilog Getting exercises, including full Verilog examples, including all documents simulation, mainly on the register definition, name mapping, RS trigger definition, etc.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
Lab01\AndOr.v
.....\Intro_Top.sct
.....\Intro_Top.spj
.....\Intro_Top.v
.....\Intro_Top.vcs
.....\Lab01_Ans\AndOr.v
.....\.........\default.cfg
.....\.........\Intro_Netlist.v
.....\.........\Intro_Top.sct
.....\.........\Intro_Top.SDF
.....\.........\Intro_Top.spj
.....\.........\Intro_Top.v
.....\.........\Intro_Top.vcs
.....\.........\Intro_TopFlat.sdf
.....\.........\Intro_TopFlat.v
.....\.........\SR.v
.....\.........\TestBench.v
.....\.........\VCS_SimRun.VCD
.....\.........\XorNor.v
.....\SR.v
.....\TestBench.v
.....\XorNor.v
.....\Lab01_Ans
Lab01