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文件名称:5_bluetooth_uart

  • 所属分类：
  • 其他小程序
  • 资源属性：
  • [VHDL] [源码]
  • 上传时间：
  • 2016-02-28
  • 文件大小：
  • 2.13mb
  • 下载次数：
  • 0次
  • 提 供 者：
  • jing*****
  • 相关连接：
  • 无
  • 下载说明：
  • 别用迅雷下载，失败请重下，重下不扣分！
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介绍说明－－下载内容均来自于网络，请自行研究使用

基于FPGA，硬件平台：basys3，软件平台：vivado。描述语言：verilog。封装自己的蓝牙串口IP。蓝牙串口数据传输需要三个模块，分别是波特率生成模块，接收模块和发送模块。-Based on the FPGA hardware platform, software platform: basys3, vivado. Descr iption: verilog. Package your own Bluetooth serial port IP. Bluetooth serial data transmission to three modules, respectively is the baud rate generation module, receiving module and sending module.
(系统自动生成,下载前可以参看下载内容)

下载文件列表





bluetooth_IP

............\clk.v

............\uart_rx.v

............\uart_top.v

............\uart_tx.v

..........uart\binbcd8.v

..............\bluetooth_top.v

..............\bluetooth_uart.xdc

..............\display.v

..............\seg7.v

bluetooth_uart

5_bluetooth_uart

................\bluetooth_uart

................\..............\bluetooth_uart.cache

................\..............\....................\compile_simlib

................\..............\....................\wt

................\..............\....................\..\java_command_handlers.wdf

................\..............\....................\..\synthesis.wdf

................\..............\....................\..\webtalk_pa.xml

................\..............\bluetooth_uart.data

................\..............\...................\constrs_1

................\..............\bluetooth_uart.hw

................\..............\.................\hw_1

................\..............\.................\....\wave

................\..............\bluetooth_uart.ioplanning

................\..............\.........................\constrs_1

................\..............\.........................\.........\designprops.xml

................\..............\.........................\.........\usercols.xml

................\..............\bluetooth_uart.runs

................\..............\...................\.jobs

................\..............\...................\.....\vrs_config_1.xml

................\..............\...................\.....\vrs_config_10.xml

................\..............\...................\.....\vrs_config_11.xml

................\..............\...................\.....\vrs_config_12.xml

................\..............\...................\.....\vrs_config_13.xml

................\..............\...................\.....\vrs_config_14.xml

................\..............\...................\.....\vrs_config_15.xml

................\..............\...................\.....\vrs_config_16.xml

................\..............\...................\.....\vrs_config_17.xml

................\..............\...................\.....\vrs_config_18.xml

................\..............\...................\.....\vrs_config_2.xml

................\..............\...................\.....\vrs_config_3.xml

................\..............\...................\.....\vrs_config_4.xml

................\..............\...................\.....\vrs_config_5.xml

................\..............\...................\.....\vrs_config_6.xml

................\..............\...................\.....\vrs_config_7.xml

................\..............\...................\.....\vrs_config_8.xml

................\..............\...................\.....\vrs_config_9.xml

................\..............\...................\UART_0_synth_1

................\..............\...................\..............\.Vivado Synthesis.queue.rst

................\..............\...................\..............\.Xil

................\..............\...................\..............\.vivado.begin.rst

................\..............\...................\..............\.vivado.end.rst

................\..............\...................\..............\ISEWrap.js

................\..............\...................\..............\ISEWrap.sh

................\..............\...................\..............\UART_0.dcp

................\..............\...................\..............\UART_0.tcl

................\..............\...................\..............\UART_0.vds

................\..............\...................\..............\UART_0_utilization_synth.pb

................\..............\...................\..............\UART_0_utilization_synth.rpt

................\..............\...................\..............\gen_run.xml

................\..............\...................\..............\htr.txt

................\..............\...................\..............\project.wdf

................\..............\...................\..............\rundef.js

................\..............\...................\.....

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