文件名称:stopwatch
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A stopwatch circuit that counts minutes and seconds, and has reset, pause functionalities. Designed using Verilog.
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下载文件列表
iseconfig
.........\clock.xreport
.........\lab3.projectmgr
_xmsgs
clock.v
controller.v
counter_min.v
counter_sec.v
display.v
extract_digits.v
fuse.xmsgs
fuseRelaunch.cmd
lab3.gise
lab3.xise
tb_clock.v
tb_counter_min.v
tb_counter_sec.v
tb_counter_sec_isim_beh1.wdb
tb_display.v
tb_extract_digits.v