文件名称:cp_model
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原创协处理模型，异步并行接口，verilog实现，可作为仿真testbench用
-Co-processing model, asynchronous parallel interface, verilog achieve, can be used as a simulation testbench
-Co-processing model, asynchronous parallel interface, verilog achieve, can be used as a simulation testbench
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下载文件列表
cp_model.v