文件名称:fenpin5_5

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [ASM] [源码]
  • 上传时间:
  • 2016-01-02
  • 文件大小:
  • 340kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • 王**
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

Verilog 语言实现利用FPGA对输入方波实现5.5分频-the frequency of a rectangular wave is divided 5.5 using the FPGA
(系统自动生成,下载前可以参看下载内容)

下载文件列表





fenpin5_5

.........\db

.........\..\fenpin5_5.asm.qmsg

.........\..\fenpin5_5.asm_labs.ddb

.........\..\fenpin5_5.cbx.xml

.........\..\fenpin5_5.cmp.bpm

.........\..\fenpin5_5.cmp.cdb

.........\..\fenpin5_5.cmp.ecobp

.........\..\fenpin5_5.cmp.hdb

.........\..\fenpin5_5.cmp.kpt

.........\..\fenpin5_5.cmp.logdb

.........\..\fenpin5_5.cmp.rdb

.........\..\fenpin5_5.cmp.tdb

.........\..\fenpin5_5.cmp0.ddb

.........\..\fenpin5_5.cmp_merge.kpt

.........\..\fenpin5_5.db_info

.........\..\fenpin5_5.eco.cdb

.........\..\fenpin5_5.eda.qmsg

.........\..\fenpin5_5.fit.qmsg

.........\..\fenpin5_5.hier_info

.........\..\fenpin5_5.hif

.........\..\fenpin5_5.lpc.html

.........\..\fenpin5_5.lpc.rdb

.........\..\fenpin5_5.lpc.txt

.........\..\fenpin5_5.map.bpm

.........\..\fenpin5_5.map.cdb

.........\..\fenpin5_5.map.ecobp

.........\..\fenpin5_5.map.hdb

.........\..\fenpin5_5.map.kpt

.........\..\fenpin5_5.map.logdb

.........\..\fenpin5_5.map.qmsg

.........\..\fenpin5_5.map_bb.cdb

.........\..\fenpin5_5.map_bb.hdb

.........\..\fenpin5_5.map_bb.logdb

.........\..\fenpin5_5.pre_map.cdb

.........\..\fenpin5_5.pre_map.hdb

.........\..\fenpin5_5.rtlv.hdb

.........\..\fenpin5_5.rtlv_sg.cdb

.........\..\fenpin5_5.rtlv_sg_swap.cdb

.........\..\fenpin5_5.sgdiff.cdb

.........\..\fenpin5_5.sgdiff.hdb

.........\..\fenpin5_5.sld_design_entry.sci

.........\..\fenpin5_5.sld_design_entry_dsc.sci

.........\..\fenpin5_5.syn_hier_info

.........\..\fenpin5_5.tan.qmsg

.........\..\fenpin5_5.tis_db_list.ddb

.........\..\fenpin5_5.tmw_info

.........\..\fenpin5_5_global_asgn_op.abo

.........\..\prev_cmp_fenpin5_5.map.qmsg

.........\..\prev_cmp_fenpin5_5.qmsg

.........\fenpin5_5.qpf

.........\fenpin5_5.qsf

.........\fenpin5_5.qws

.........\fenpin5_5.v

.........\fenpin5_5.v.bak

.........\incremental_db

.........\..............\compiled_partitions

.........\..............\...................\fenpin5_5.root_partition.cmp.atm

.........\..............\...................\fenpin5_5.root_partition.cmp.dfp

.........\..............\...................\fenpin5_5.root_partition.cmp.hdbx

.........\..............\...................\fenpin5_5.root_partition.cmp.kpt

.........\..............\...................\fenpin5_5.root_partition.cmp.logdb

.........\..............\...................\fenpin5_5.root_partition.cmp.rcf

.........\..............\...................\fenpin5_5.root_partition.map.atm

.........\..............\...................\fenpin5_5.root_partition.map.dpi

.........\..............\...................\fenpin5_5.root_partition.map.hdbx

.........\..............\...................\fenpin5_5.root_partition.map.kpt

.........\..............\README

.........\release

.........\.......\fenpin5_5.asm.rpt

.........\.......\fenpin5_5.done

.........\.......\fenpin5_5.eda.rpt

.........\.......\fenpin5_5.fit.rpt

.........\.......\fenpin5_5.fit.smsg

.........\.......\fenpin5_5.fit.summary

.........\.......\fenpin5_5.flow.rpt

.........\.......\fenpin5_5.map.rpt

.........\.......\fenpin5_5.map.summary

.........\.......\fenpin5_5.pin

.........\.......\fenpin5_5.pof

.........\.......\fenpin5_5.sof

.........\.......\fenpin5_5.tan.rpt

.........\.......\fenpin5_5.tan.summary

.........\simulation

.........\..........\modelsim

.........\..........\........\fenpin5_5.sft

.........\..........\........\fenpin5_5.vho

.........\..........\........\fenpin5_5_modelsim.xrf

.........\..........\........\fenpin5_5_test.cr.mti

.........\..........\........\fenpin5_5_test.mpf

.........\..........\........\fenpin5_5_test.v

.........\..........\........\fenpin5_5_test.v.bak

.........\..........\........\fenpin5_5_vhd.sdo

.........\..........\........\vsim.wlf

.........\..........\........\work

.........\..........\........\....\fenpin5_5

.........\..........\........\....\.........\verilog.asm

.........\..........\........\....\.........\verilog.rw

.........\..........\........\....\.........\_primary.dat

.........\..........\........\....\.........\_primary.dbs

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