文件名称:18_uart

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [VHDL] [源码]
  • 上传时间:
  • 2015-12-22
  • 文件大小:
  • 5.78mb
  • 下载次数:
  • 0次
  • 提 供 者:
  • adel****
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

FPGA的串口程序,有串口控制器,串口发送,串口接收模块和顶层测试 模块等。-verilog code about the FPGA uart module.
(系统自动生成,下载前可以参看下载内容)

下载文件列表





18_uart\db\altsyncram_mnf1.tdf

.......\..\a_dpfifo_6q71.tdf

.......\..\cmpr_hs8.tdf

.......\..\cntr_9a7.tdf

.......\..\cntr_s9b.tdf

.......\..\cntr_t9b.tdf

.......\..\logic_util_heursitic.dat

.......\..\prev_cmp_uart.qmsg

.......\..\scfifo_vj71.tdf

.......\..\uart.amm.cdb

.......\..\uart.asm.qmsg

.......\..\uart.asm.rdb

.......\..\uart.asm_labs.ddb

.......\..\uart.cbx.xml

.......\..\uart.cmp.bpm

.......\..\uart.cmp.cdb

.......\..\uart.cmp.hdb

.......\..\uart.cmp.kpt

.......\..\uart.cmp.logdb

.......\..\uart.cmp.rdb

.......\..\uart.cmp_merge.kpt

.......\..\uart.cycloneive_io_sim_cache.31um_ff_1200mv_0c_fast.hsd

.......\..\uart.cycloneive_io_sim_cache.31um_ss_1200mv_0c_slow.hsd

.......\..\uart.cycloneive_io_sim_cache.31um_ss_1200mv_85c_slow.hsd

.......\..\uart.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd

.......\..\uart.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd

.......\..\uart.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd

.......\..\uart.db_info

.......\..\uart.fit.qmsg

.......\..\uart.hier_info

.......\..\uart.hif

.......\..\uart.idb.cdb

.......\..\uart.lpc.html

.......\..\uart.lpc.rdb

.......\..\uart.lpc.txt

.......\..\uart.map.bpm

.......\..\uart.map.cdb

.......\..\uart.map.hdb

.......\..\uart.map.kpt

.......\..\uart.map.logdb

.......\..\uart.map.qmsg

.......\..\uart.map_bb.cdb

.......\..\uart.map_bb.hdb

.......\..\uart.map_bb.logdb

.......\..\uart.pre_map.cdb

.......\..\uart.pre_map.hdb

.......\..\uart.rpp.qmsg

.......\..\uart.rtlv.hdb

.......\..\uart.rtlv_sg.cdb

.......\..\uart.rtlv_sg_swap.cdb

.......\..\uart.sgate.rvd

.......\..\uart.sgate_sm.rvd

.......\..\uart.sgdiff.cdb

.......\..\uart.sgdiff.hdb

.......\..\uart.sld_design_entry.sci

.......\..\uart.sld_design_entry_dsc.sci

.......\..\uart.smart_action.txt

.......\..\uart.sta.qmsg

.......\..\uart.sta.rdb

.......\..\uart.sta_cmp.8_slow_1200mv_85c.tdb

.......\..\uart.syn_hier_info

.......\..\uart.tiscmp.fastest_slow_1200mv_0c.ddb

.......\..\uart.tiscmp.fastest_slow_1200mv_85c.ddb

.......\..\uart.tiscmp.fast_1200mv_0c.ddb

.......\..\uart.tiscmp.slow_1200mv_0c.ddb

.......\..\uart.tiscmp.slow_1200mv_85c.ddb

.......\..\uart.tis_db_list.ddb

.......\..\uart.tmw_info

.......\greybox_tmp\cbx_args.txt

.......\incremental_db\compiled_partitions\uart.db_info

.......\..............\...................\uart.root_partition.cmp.cdb

.......\..............\...................\uart.root_partition.cmp.dfp

.......\..............\...................\uart.root_partition.cmp.hdb

.......\..............\...................\uart.root_partition.cmp.kpt

.......\..............\...................\uart.root_partition.cmp.logdb

.......\..............\...................\uart.root_partition.cmp.rcfdb

.......\..............\...................\uart.root_partition.map.cdb

.......\..............\...................\uart.root_partition.map.dpi

.......\..............\...................\uart.root_partition.map.hbdb.cdb

.......\..............\...................\uart.root_partition.map.hbdb.hb_info

.......\..............\...................\uart.root_partition.map.hbdb.hdb

.......\..............\...................\uart.root_partition.map.hbdb.sig

.......\..............\...................\uart.root_partition.map.hdb

.......\..............\...................\uart.root_partition.map.kpt

.......\..............\README

.......\rx_fifo_module.qip

.......\source\detect_module.v

.......\......\inter_control_module.v

.......\......\rx_bps_module.v

.......\......\rx_bps_module.v.bak

.......\......\rx_control_module.v

.......\......\rx_fifo_module.qip

.......\......\rx_fifo_module.v

.......\......\rx_fifo_module_bb.v

.......\......\rx_fifo_module_inst.v

.......\......\rx_interface.v

.......\......\rx_module.v

.......\......\rx_top_control_module.v

.......\......\rx_tx_interface_demo.v

.......\......\tx_bps_module.v

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