文件名称:DES_verilog
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用verilog实现的DES(Data Encryption Standard数据加密标准)，把64位明文输入变为64位密文输出块。-Using DES (Data Encryption Standard Data Encryption Standard) verilog to achieve, the 64 plaintext input into 64 output ciphertext block.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
11.1
....\chart
....\.....\Thumbs.db
....\.....\图11-12.bmp
....\.....\图11-13.bmp
....\.....\图11-14.bmp
....\.....\图11-15.bmp
....\.....\图11-16.bmp
....\.....\图11-19.bmp
....\.....\图11-20.bmp
....\.....\图11-5.bmp
....\.....\图11-6.bmp
....\.....\图11-8.bmp
....\.....\图11-9.bmp
....\.....\表11-1.bmp
....\.....\表11-2.bmp
....\.....\表11-3.bmp
....\.....\表11-4.bmp
....\.....\表11-5.bmp
....\.....\表11-6.bmp
....\.....\表11-8.bmp
....\.....\表11-9.bmp
....\des.cr.mti
....\des.mpf
....\des.v
....\des_testbench.v
....\desround.v
....\key_gen.v
....\s1.v
....\s2.v
....\s3.v
....\s4.v
....\s5.v
....\s6.v
....\s7.v
....\s8.v
....\transcript
....\vsim.wlf
....\wave
....\....\Thumbs.db
....\....\des.bmp
....\....\des_testbench.bmp
....\....\desround.bmp
....\....\key_gen.bmp
....\....\s1~s8.bmp
....\wb_descontroller.v
....\work
....\....\_info
....\....\des
....\....\...\_primary.dat
....\....\...\_primary.vhd
....\....\...\verilog.asm
....\....\des_testbench
....\....\.............\_primary.dat
....\....\.............\_primary.vhd
....\....\.............\verilog.asm
....\....\des_top
....\....\.......\_primary.dat
....\....\.......\_primary.vhd
....\....\.......\verilog.asm
....\....\desround
....\....\........\_primary.dat
....\....\........\_primary.vhd
....\....\........\verilog.asm
....\....\key_gen
....\....\.......\_primary.dat
....\....\.......\_primary.vhd
....\....\.......\verilog.asm
....\....\s1
....\....\..\_primary.dat
....\....\..\_primary.vhd
....\....\..\verilog.asm
....\....\s2
....\....\..\_primary.dat
....\....\..\_primary.vhd
....\....\..\verilog.asm
....\....\s3
....\....\..\_primary.dat
....\....\..\_primary.vhd
....\....\..\verilog.asm
....\....\s4
....\....\..\_primary.dat
....\....\..\_primary.vhd
....\....\..\verilog.asm
....\....\s5
....\....\..\_primary.dat
....\....\..\_primary.vhd
....\....\..\verilog.asm
....\....\s6
....\....\..\_primary.dat
....\....\..\_primary.vhd
....\....\..\verilog.asm
....\....\s7
....\....\..\_primary.dat
....\....\..\_primary.vhd
....\....\..\verilog.asm
....\....\s8
....\....\..\_primary.dat
....\....\..\_primary.vhd
....\....\..\verilog.asm