ADF4350 配置的verilog hdl程序，模块化设计，输入待配置的数据，启动信号，即可自动产生时序，完成一次配置，模块还有done握手信号，方便用户调用时，反复多次配置-Allocation of ADF4350 Verilog HDL program, modular design, input the data to be configured, start signal, can automatically generate timing, complete the configuration, module and done handshake signals, convenient user calls, repeatedly configuration