文件名称:QPSK
介绍说明－－下载内容均来自于网络，请自行研究使用
这是关于QPSK调制解调的VerilogHDL语言的代码，还有用Modelsim仿真的工程文件。testbench都已经写好了。-This is the QPSK modulation and demodulation of VerilogHDL language code, as well as with Modelsim simulation project file. testbench have been written.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
QPSK
....\QPSK_demodulator
....\................\design
....\................\......\QPSK_demodulator.v
....\................\......\test.v
....\................\test.cr.mti
....\................\test.mpf
....\................\vsim.wlf
....\................\work
....\................\....\@q@p@s@k_demodulator
....\................\....\....................\_primary.dat
....\................\....\....................\_primary.dbs
....\................\....\....................\_primary.vhd
....\................\....\....................\verilog.asm
....\................\....\....................\verilog.rw
....\................\....\_info
....\................\....\_temp
....\................\....\.....\vlog6cmg17
....\................\....\_vmake
....\................\....\test
....\................\....\....\_primary.dat
....\................\....\....\_primary.dbs
....\................\....\....\_primary.vhd
....\................\....\....\verilog.asm
....\................\....\....\verilog.rw
....\QPSK_modulator
....\..............\design
....\..............\......\QPSK_modulator.v
....\..............\......\test.v
....\..............\test.cr.mti
....\..............\test.mpf
....\..............\test.v.bak
....\..............\vsim.wlf
....\..............\work
....\..............\....\@q@p@s@k_modulator
....\..............\....\..................\_primary.dat
....\..............\....\..................\_primary.dbs
....\..............\....\..................\_primary.vhd
....\..............\....\..................\verilog.asm
....\..............\....\..................\verilog.rw
....\..............\....\_info
....\..............\....\_temp
....\..............\....\.....\vlog5vj5w0
....\..............\....\.....\vlogckv4sk
....\..............\....\_vmake
....\..............\....\test
....\..............\....\....\_primary.dat
....\..............\....\....\_primary.dbs
....\..............\....\....\_primary.vhd
....\..............\....\....\verilog.asm
....\..............\....\....\verilog.rw