RISC_CPU\pre_sim\alu.v

........\.......\alu.v.bak

........\.......\clk_gen.v

........\.......\cpu_top.v

........\.......\data_ram.v

........\.......\data_ram.v.bak

........\.......\pc_cnt.v

........\.......\pc_cnt.v.bak

........\.......\pc_rom.v

........\.......\pc_rom.v.bak

........\.......\register.v

........\.......\risc_cpu.cr.mti

........\.......\risc_cpu.mpf

........\.......\risc_cpu.v

........\.......\vsim.wlf

........\.......\work\_info

........\.......\....\_vmake

........\.......\....\.temp\vlog0gfn2g

........\.......\....\@r@i@s@c_@c@p@u\verilog.asm

........\.......\....\...............\verilog.rw

........\.......\....\...............\_primary.dat

........\.......\....\...............\_primary.dbs

........\.......\....\...............\_primary.vhd

........\.......\....\...e@g@i@s@t@e@r\verilog.asm

........\.......\....\................\verilog.rw

........\.......\....\................\_primary.dat

........\.......\....\................\_primary.dbs

........\.......\....\................\_primary.vhd

........\.......\....\.p@c_@r@o@m\verilog.asm

........\.......\....\...........\verilog.rw

........\.......\....\...........\_primary.dat

........\.......\....\...........\_primary.dbs

........\.......\....\...........\_primary.vhd

........\.......\....\......c@n@t\verilog.asm

........\.......\....\...........\verilog.rw

........\.......\....\...........\_primary.dat

........\.......\....\...........\_primary.dbs

........\.......\....\...........\_primary.vhd

........\.......\....\.d@a@t@a_@r@a@m\verilog.asm

........\.......\....\...............\verilog.rw

........\.......\....\...............\_primary.dat

........\.......\....\...............\_primary.dbs

........\.......\....\...............\_primary.vhd

........\.......\....\.c@p@u_@t@o@p\verilog.asm

........\.......\....\.............\verilog.rw

........\.......\....\.............\_primary.dat

........\.......\....\.............\_primary.dbs

........\.......\....\.............\_primary.vhd

........\.......\....\...l@k_@g@e@n\verilog.asm

........\.......\....\.............\verilog.rw

........\.......\....\.............\_primary.dat

........\.......\....\.............\_primary.dbs

........\.......\....\.............\_primary.vhd

........\.......\....\.a@l@u\verilog.asm

........\.......\....\......\verilog.rw

........\.......\....\......\_primary.dat

........\.......\....\......\_primary.dbs

........\.......\....\......\_primary.vhd

........\.......\report\report.txt

........\.ost_sim\cpu_top.v

........\........\risc_cpu.sdf

........\........\risc_cpu_netlist.v

........\dc\command.log

........\..\default.svf

........\..\filenames.log

........\..\risc_cpu.sdf

........\..\risc_cpu_netlist.v

........\..\verilog\alu.v

........\..\.......\clk_gen.v

........\..\.......\cpu_top.v

........\..\.......\data_ram.v

........\..\.......\pc_cnt.v

........\..\.......\pc_rom.v

........\..\.......\register.v

........\..\.......\risc_cpu.v

........\..\.......\transcript

........\..\report\area.txt

........\..\......\constraint.txt

........\..\......\timing.txt

........\..\ddc\ALU.ddc

........\..\...\ALU_DW01_add_0.ddc

........\..\...\ALU_DW01_add_1.ddc

........\..\...\ALU_DW01_inc_0.ddc

........\..\...\ALU_DW01_sub_0.ddc

........\..\...\CLK_GEN.ddc

........\..\...\jizheshanchu.db.ddc

........\..\...\PC_CNT.ddc

........\..\...\PC_CNT_DW01_inc_0.ddc

........\..\...\PC_CNT_DW01_inc_1.ddc

........\..\...\REGISTER.ddc

........\..\...\RISC_CPU.ddc

........\pre_sim\work\_temp

........\.......\....\@r@i@s@c_@c@p@u

........\.......\....\@r@e@g@i@s@t@e@r

........\.......\....\@p@c_@r@o@m

........\.......\....\@p@c_@c@n@t

........\.......\....\@d@a@t@a_@r@a@m

........\.......\....\@c@p@u_@t@o@p

........\.......\....\@c@l@k_@g@e@n

........\.......\....\@a@l@u