文件名称:SOC_Code

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • 上传时间:
  • 2015-05-17
  • 文件大小:
  • 92kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • dan****
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

加法器,原码补码乘法器,ROM设计,PC计数器等的VHDL详细代码-The source-code complement adder, multiplier, ROM design, such as PC counter of VHDL code in detail
(系统自动生成,下载前可以参看下载内容)

下载文件列表





SOC_Code设计实践\SOC_Code\01_串行加法器\cxjfq.ucf

................\........\.............\cxjfq.vhd

................\........\.2_并行加法器\bxjfq.ucf

................\........\.............\bxjfq.vhd

................\........\.3_数码管显示模块\data2seg.vhd

................\........\.................\seg_dis.vhd

................\........\.................\seg_dis_keyin.vhd

................\........\.................\smg.ucf

................\........\.4_原码两位乘\mul2.vhd

................\........\.5_布斯乘法器\ComplementalCodeMultiplexer8b.ucf

................\........\.............\ComplementalCodeMultiplexer8b.vhd

................\........\.6_阵列乘法器\and_2.vhd

................\........\.............\fau.vhd

................\........\.............\low_row.vhd

................\........\.............\mid_row.vhd

................\........\.............\mul8_0.vhd

................\........\.............\mul8_o.ucf

................\........\.............\test.vhd

................\........\.............\top_row.vhd

................\........\.7_加减交替除法器\a.ucf

................\........\.................\div.vhd

................\........\.8_ROM存储器\data2seg.vhd

................\........\............\myUCF.ucf

................\........\............\ROM.vhd

................\........\............\romfile.dat

................\........\............\seg_dis.vhd

................\........\............\top.vhd

................\........\.9_FIFO存储器\data2seg.vhd

................\........\.............\fifio_tb.vhd

................\........\.............\fifo_top.vhd

................\........\.............\myUCF.ucf

................\........\.............\seg_dis.vhd

................\........\.............\seg_dis_keyin.vhd

................\........\10_时钟模块设计\clk_gen.vhd

................\........\...............\testbench.vhd

................\........\.1_PC程序计数器设计\data2seg.vhd

................\........\...................\myUCF.ucf

................\........\...................\pc.vhd

................\........\...................\seg_dis.vhd

................\........\...................\seg_dis_keyin.vhd

................\........\.2_程序存储器ROM(4KB)\data2seg.vhd

................\........\.......................\myUCF.ucf

................\........\.......................\ROM.vhd

................\........\.......................\romfile.dat

................\........\.......................\seg_dis.vhd

................\........\.......................\top.vhd

................\........\.3_IR_Resgister\data2seg.vhd

................\........\...............\IR_module.vhd

................\........\...............\myUCF.ucf

................\........\...............\seg_dis.vhd

................\........\...............\seg_dis_keyin.vhd

................\........\.4_RN_Resgister\data2seg.vhd

................\........\...............\module_Rn.vhd

................\........\...............\myUCF.ucf

................\........\...............\seg_dis.vhd

................\........\...............\seg_dis_keyin.vhd

................\........\.5_算数逻辑单元ALU设计\data2seg.vhd

................\........\......................\myUCF.ucf

................\........\......................\seg_dis.vhd

................\........\......................\seg_dis_keyin.vhd

................\........\......................\unit74181.vhd

................\........\.6_数据存储器RAM设计\data2seg.vhd

................\........\....................\module_ram.vhd

................\........\....................\module_ram_tb.vhd

................\........\....................\myUCF.ucf

................\........\....................\seg_dis.vhd

................\........\....................\seg_dis_keyin.vhd

................\........\.7_堆栈指针SP设计\data2seg.vhd

................\........\.................\frediv.vhd

................\........\.................\module_sp.vhd

................\........\.................\myUCF.ucf

................\........\.................\seg_dis.vhd

................\........\.................\seg_dis_keyin.vhd

......

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