文件名称:r7lite
介绍说明－－下载内容均来自于网络，请自行研究使用
R7Lite是基于Xilinx的Kintex7系列FPGA的PCI Express参考设计代码，PCIe 2.0 4x模式，包括了FPGA实现，Linux下驱动和测试例程。-R7Lite is a PCIe Reference design based on Xilinx Kintex7 FPGA,including FPGA code ,Linux Driver and Testing App
(系统自动生成,下载前可以参看下载内容)
下载文件列表
ddr3_source
...........\clocking
...........\........\mig_7series_v1_9_clk_ibuf.v
...........\........\mig_7series_v1_9_infrastructure.v
...........\........\mig_7series_v1_9_iodelay_ctrl.v
...........\........\mig_7series_v1_9_tempmon.v
...........\controller
...........\..........\mig_7series_v1_9_arb_mux.v
...........\..........\mig_7series_v1_9_arb_row_col.v
...........\..........\mig_7series_v1_9_arb_select.v
...........\..........\mig_7series_v1_9_bank_cntrl.v
...........\..........\mig_7series_v1_9_bank_common.v
...........\..........\mig_7series_v1_9_bank_compare.v
...........\..........\mig_7series_v1_9_bank_mach.v
...........\..........\mig_7series_v1_9_bank_queue.v
...........\..........\mig_7series_v1_9_bank_state.v
...........\..........\mig_7series_v1_9_col_mach.v
...........\..........\mig_7series_v1_9_mc.v
...........\..........\mig_7series_v1_9_rank_cntrl.v
...........\..........\mig_7series_v1_9_rank_common.v
...........\..........\mig_7series_v1_9_rank_mach.v
...........\..........\mig_7series_v1_9_round_robin_arb.v
...........\ddr3_driver.v
...........\ddr3_ip.v
...........\ecc
...........\...\mig_7series_v1_9_ecc_buf.v
...........\...\mig_7series_v1_9_ecc_dec_fix.v
...........\...\mig_7series_v1_9_ecc_gen.v
...........\...\mig_7series_v1_9_ecc_merge_enc.v
...........\example_top.ucf
...........\ip_top
...........\......\mig_7series_v1_9_memc_ui_top_std.v
...........\......\mig_7series_v1_9_mem_intfc.v
...........\phy
...........\...\mig_7series_v1_9_ddr_byte_group_io.v
...........\...\mig_7series_v1_9_ddr_byte_lane.v
...........\...\mig_7series_v1_9_ddr_calib_top.v
...........\...\mig_7series_v1_9_ddr_if_post_fifo.v
...........\...\mig_7series_v1_9_ddr_mc_phy.v
...........\...\mig_7series_v1_9_ddr_mc_phy_wrapper.v
...........\...\mig_7series_v1_9_ddr_of_pre_fifo.v
...........\...\mig_7series_v1_9_ddr_phy_4lanes.v
...........\...\mig_7series_v1_9_ddr_phy_ck_addr_cmd_delay.v
...........\...\mig_7series_v1_9_ddr_phy_dqs_found_cal.v
...........\...\mig_7series_v1_9_ddr_phy_dqs_found_cal_hr.v
...........\...\mig_7series_v1_9_ddr_phy_init.v
...........\...\mig_7series_v1_9_ddr_phy_oclkdelay_cal.v
...........\...\mig_7series_v1_9_ddr_phy_prbs_rdlvl.v
...........\...\mig_7series_v1_9_ddr_phy_rdlvl.v
...........\...\mig_7series_v1_9_ddr_phy_tempmon.v
...........\...\mig_7series_v1_9_ddr_phy_top.v
...........\...\mig_7series_v1_9_ddr_phy_wrcal.v
...........\...\mig_7series_v1_9_ddr_phy_wrlvl.v
...........\...\mig_7series_v1_9_ddr_phy_wrlvl_off_delay.v
...........\...\mig_7series_v1_9_ddr_prbs_gen.v
...........\sim
...........\...\ddr3_model.v
...........\...\ddr3_model_parameters.vh
...........\...\isim_files.prj
...........\...\isim_options.tcl
...........\...\isim_run.bat
...........\...\readme.txt
...........\...\sim.do
...........\...\sim_tb_top.v
...........\...\wiredly.v
...........\...\xsim_files.prj
...........\...\xsim_options.tcl
...........\...\xsim_run.bat
...........\ui
...........\..\mig_7series_v1_9_ui_cmd.v
...........\..\mig_7series_v1_9_ui_rd_data.v
...........\..\mig_7series_v1_9_ui_top.v
...........\..\mig_7series_v1_9_ui_wr_data.v
doc
...\adaloop_pin
...\control_reg
ipcore_dir
..........\.ncf
..........\coregen.cgp
..........\counter_fifo
..........\............\doc
..........\............\...\fifo_generator_v9_3_readme.txt
..........\............\...\fifo_generator_v9_3_vinfo.html
..........\............\...\pg057-fifo-generator.pdf
..........\............\example_design
..........\............\..............\counter_fifo_exdes.ucf
..........\............\..............\counter_fifo_exdes.vhd
..........\............\fifo_generator_v9_3_readme.txt
..........\............\implement
..........\............\.........\implement.bat
..........\............\.........\implement.sh
..........\............\.........\implement_synplify.bat
..........\............\.........\implement_synplify.sh
..........\............\.........\planAhead_ise.bat
..........\............\.........\planAhead_ise.sh
..........\............\.........\planAhead_ise.tcl
..........\............\.........\xst.prj
.......