文件名称:shuzizhong
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基于VHDL语言的数字钟，有元件例化，修改时钟功能 Quartus II平台-VHDL language based digital clock, there are component instantiation, modify clock function Quartus II platform
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下载文件列表
shuzizhong\clk11.bdf
..........\clk11.qpf
..........\clk11.qsf
..........\clk11.qws
..........\clk11.vhd
..........\clk11.vhd.bak
..........\clk11_nativelink_simulation.rpt
..........\db\clk11.asm.qmsg
..........\..\clk11.asm.rdb
..........\..\clk11.cbx.xml
..........\..\clk11.cmp.bpm
..........\..\clk11.cmp.cdb
..........\..\clk11.cmp.hdb
..........\..\clk11.cmp.idb
..........\..\clk11.cmp.kpt
..........\..\clk11.cmp.logdb
..........\..\clk11.cmp.rdb
..........\..\clk11.cmp0.ddb
..........\..\clk11.cmp_merge.kpt
..........\..\clk11.db_info
..........\..\clk11.eda.qmsg
..........\..\clk11.fit.qmsg
..........\..\clk11.hier_info
..........\..\clk11.hif
..........\..\clk11.ipinfo
..........\..\clk11.lpc.html
..........\..\clk11.lpc.rdb
..........\..\clk11.lpc.txt
..........\..\clk11.map.ammdb
..........\..\clk11.map.bpm
..........\..\clk11.map.cdb
..........\..\clk11.map.hdb
..........\..\clk11.map.kpt
..........\..\clk11.map.logdb
..........\..\clk11.map.qmsg
..........\..\clk11.map.rdb
..........\..\clk11.map_bb.cdb
..........\..\clk11.map_bb.hdb
..........\..\clk11.map_bb.logdb
..........\..\clk11.pplq.rdb
..........\..\clk11.pre_map.hdb
..........\..\clk11.pti_db_list.ddb
..........\..\clk11.root_partition.map.reg_db.cdb
..........\..\clk11.routing.rdb
..........\..\clk11.rpp.qmsg
..........\..\clk11.rtlv.hdb
..........\..\clk11.rtlv_sg.cdb
..........\..\clk11.rtlv_sg_swap.cdb
..........\..\clk11.sgate.rvd
..........\..\clk11.sgate_sm.rvd
..........\..\clk11.sgdiff.cdb
..........\..\clk11.sgdiff.hdb
..........\..\clk11.sld_design_entry.sci
..........\..\clk11.sld_design_entry_dsc.sci
..........\..\clk11.smart_action.txt
..........\..\clk11.sta.qmsg
..........\..\clk11.sta.rdb
..........\..\clk11.sta_cmp.8_slow.tdb
..........\..\clk11.stingray_io_sim_cache.99um_ff_1200mv_0c_fast.hsd
..........\..\clk11.stingray_io_sim_cache.99um_tt_1200mv_0c_slow.hsd
..........\..\clk11.stingray_io_sim_cache.99um_tt_1200mv_85c_slow.hsd
..........\..\clk11.syn_hier_info
..........\..\clk11.tis_db_list.ddb
..........\..\clk11.tmw_info
..........\..\clk11.vpr.ammdb
..........\..\logic_util_heursitic.dat
..........\..\prev_cmp_clk11.qmsg
..........\HOUR_24.bsf
..........\HOUR_24.vhd
..........\HOUR_24.vhd.bak
..........\incremental_db\compiled_partitions\clk11.db_info
..........\..............\...................\clk11.root_partition.cmp.ammdb
..........\..............\...................\clk11.root_partition.cmp.cdb
..........\..............\...................\clk11.root_partition.cmp.dfp
..........\..............\...................\clk11.root_partition.cmp.hdb
..........\..............\...................\clk11.root_partition.cmp.kpt
..........\..............\...................\clk11.root_partition.cmp.logdb
..........\..............\...................\clk11.root_partition.cmp.rcfdb
..........\..............\...................\clk11.root_partition.map.cdb
..........\..............\...................\clk11.root_partition.map.dpi
..........\..............\...................\clk11.root_partition.map.hbdb.cdb
..........\..............\...................\clk11.root_partition.map.hbdb.hb_info
..........\..............\...................\clk11.root_partition.map.hbdb.hdb
..........\..............\...................\clk11.root_partition.map.hbdb.sig
..........\..............\...................\clk11.root_partition.map.hdb
..........\..............\...................\clk11.root_partition.map.kpt
..........\..............\README
..........\led1.vhd
..........\led1.vhd.bak
..........\MIN_60.bsf
..........\MIN_60.vhd
..........\MIN_60.vhd.bak
..........\output_files\clk11.asm.rpt
..........\............\clk11.cdf
..........\............\clk11.done
..........\............\clk11.eda.rpt
..........\............\clk11.fit.rpt
..........\............\clk11.fit.smsg
..........\............\clk11.fit.summary
..........\............\clk11.flow.rpt