文件名称:TLC1620
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基于FPGA的Verilog语言实现的六十进制计数器-FPGA-based Verilog language implementation of six decimal counter
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下载文件列表
TLC1620\1650fa.pdf
.......\alterapll.v
.......\alterapll.v.bak
.......\DA_Serial_TIMING.v
.......\DA_Serial_TIMING.v.bak
.......\DA_TLC.cr.mti
.......\DA_TLC.mpf
.......\TLC_tb.v
.......\TLC_tb.v.bak
.......\vsim.wlf
.......\work\@d@a_@serial_@t@i@m@i@n@g\verilog.asm64
.......\....\.........................\verilog.rw64
.......\....\.........................\_primary.dat
.......\....\.........................\_primary.dbs
.......\....\.........................\_primary.vhd
.......\....\alterapll\verilog.asm64
.......\....\.........\verilog.rw64
.......\....\.........\_primary.dat
.......\....\.........\_primary.dbs
.......\....\.........\_primary.vhd
.......\....\tb\verilog.asm64
.......\....\..\verilog.rw64
.......\....\..\_primary.dat
.......\....\..\_primary.dbs
.......\....\..\_primary.vhd
.......\....\_info
.......\....\.temp\vlogbnd6he
.......\....\.....\vlogviqt68
.......\....\_vmake
.......\....\@d@a_@serial_@t@i@m@i@n@g
.......\....\alterapll
.......\....\tb
.......\....\_temp
.......\work
TLC1620