文件名称:6luqiangda
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六路抢答器，保证抢答模块绝对一输出，无后门。-All the buzzer, an absolute guarantee that vies to answer first module output, no back door.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
6luqiangda\db\add_sub_lkc.tdf
..........\..\add_sub_mkc.tdf
..........\..\alt_u_div_i2f.tdf
..........\..\eda_design.cbx.xml
..........\..\eda_design.cmp.rdb
..........\..\eda_design.cmp_merge.kpt
..........\..\eda_design.db_info
..........\..\eda_design.eco.cdb
..........\..\eda_design.eds_overflow
..........\..\eda_design.fit.qmsg
..........\..\eda_design.fnsim.hdb
..........\..\eda_design.fnsim.qmsg
..........\..\eda_design.hier_info
..........\..\eda_design.hif
..........\..\eda_design.lpc.html
..........\..\eda_design.lpc.rdb
..........\..\eda_design.lpc.txt
..........\..\eda_design.map.bpm
..........\..\eda_design.map.cdb
..........\..\eda_design.map.ecobp
..........\..\eda_design.map.hdb
..........\..\eda_design.map.kpt
..........\..\eda_design.map.logdb
..........\..\eda_design.map.qmsg
..........\..\eda_design.map_bb.cdb
..........\..\eda_design.map_bb.hdb
..........\..\eda_design.map_bb.logdb
..........\..\eda_design.pre_map.cdb
..........\..\eda_design.pre_map.hdb
..........\..\eda_design.rtlv.hdb
..........\..\eda_design.rtlv_sg.cdb
..........\..\eda_design.rtlv_sg_swap.cdb
..........\..\eda_design.sgdiff.cdb
..........\..\eda_design.sgdiff.hdb
..........\..\eda_design.sim.cvwf
..........\..\eda_design.sim.qmsg
..........\..\eda_design.sim.rdb
..........\..\eda_design.simfam
..........\..\eda_design.sld_design_entry.sci
..........\..\eda_design.sld_design_entry_dsc.sci
..........\..\eda_design.syn_hier_info
..........\..\eda_design.tis_db_list.ddb
..........\..\lpm_divide_h6m.tdf
..........\..\mux_3nc.tdf
..........\..\mux_joc.tdf
..........\..\mux_umc.tdf
..........\..\prev_cmp_eda_design.fit.qmsg
..........\..\prev_cmp_eda_design.map.qmsg
..........\..\prev_cmp_eda_design.qmsg
..........\..\prev_cmp_eda_design.sim.qmsg
..........\..\sign_div_unsign_olh.tdf
..........\..\wed.wsf
..........\div_1s.bsf
..........\div_1s.v
..........\div_1s.v.bak
..........\eda_design.bdf
..........\eda_design.done
..........\eda_design.dpf
..........\eda_design.fit.rpt
..........\eda_design.fit.summary
..........\eda_design.flow.rpt
..........\eda_design.map.rpt
..........\eda_design.map.smsg
..........\eda_design.map.summary
..........\eda_design.qpf
..........\eda_design.qsf
..........\eda_design.qws
..........\eda_design.sim.rpt
..........\eda_design.vwf
..........\fenpin_2k.bsf
..........\fenpin_2k.v
..........\incremental_db\compiled_partitions\eda_design.root_partition.map.atm
..........\..............\...................\eda_design.root_partition.map.dpi
..........\..............\...................\eda_design.root_partition.map.hdbx
..........\..............\...................\eda_design.root_partition.map.kpt
..........\..............\README
..........\jifen1_6.bsf
..........\jifen1_6.v
..........\jifen1_6.v.bak
..........\jishi_9s.bsf
..........\jishi_9s.v
..........\led_show.bsf
..........\led_show.v
..........\led_show.v.bak
..........\qiangda.bsf
..........\qiangda.v
..........\qiangda.v.bak
..........\warn.bsf
..........\warn.v
..........\incremental_db\compiled_partitions
..........\db
..........\incremental_db
6luqiangda